Memory latency reduction via thread throttling

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 53-64

  Cheng, Hsiang Yun ^a   Lin, Chung Hsiang ^a   Li, Jian ^b   Yang, Chia Lin ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; APPLICATION THREADS; CPU CORES; GEOMETRIC MEAN; MEMORY ACCESS; MEMORY LATENCIES; MEMORY RESOURCES; MEMORY WALL; MULTICORE ARCHITECTURES; PERFORMANCE IMPROVEMENTS; PHASE BASED; PHASE DETECTION; PROCESSOR PERFORMANCE; REAL-WORLD APPLICATION; RUN-TIME SCHEDULING; RUNTIMES; SYNTHETIC WORKLOADS; THROTTLING MECHANISM; WORKLOAD VARIATION;

COMPUTER SIMULATION; LAKES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MODELS; SCHEDULING;

MEMORY ARCHITECTURE;

EID: 79951707102     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.39     Document Type: Conference Paper

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