Asynchronous DRAM design and synthesis

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2003, Pages 174-183

  Ekanayake, Virantha N ^a   Manohar, Rajit ^a  

^a Cornell University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT DESIGN;

ACCESS LATENCY; ASYNCHRONOUS CONTROL CIRCUITS; CYCLE TIME; DRAM DESIGN; LOGIC PROCESS; LONG CYCLE TIME; ON CHIPS; PERFORMANCE; QUASI DELAY INSENSITIVE; SUBNANOSECOND;

DELAY CIRCUITS;

EID: 2942632886     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2003.1199177     Document Type: Conference Paper

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