65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing

2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications

Volumn , Issue , 2012, Pages 21-24

  Yu, Theodore ^a,c   Park, Jongkil ^a,c   Joshi, Siddharth ^a,c   Maier, Christoph ^a,c   Cauwenberghs, Gert ^b,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA SAN DIEGO   (United States)

^c UNIVERSITY OF CALIFORNIA SAN DIEGO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CONTROLS; ARRAY TRANSCEIVERS; EVENT-DRIVEN; INTEGRATE AND FIRES; INTEGRATE-AND-FIRE NEURONS; MEASUREMENTS OF; MIXED SIGNAL; NEURAL MODELS; RECONFIGURABLE; SYNAPTIC CONNECTIVITY; SYNAPTIC EVENTS; SYNAPTIC INPUT; TIME MULTIPLEXED;

TRANSCEIVERS; VLSI CIRCUITS;

NEURONS;

EID: 84874143086     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BioCAS.2012.6418479     Document Type: Conference Paper

References (16)

1. R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, L. Camunas-Mesa, R. Berner, M. Rivas-Perez, T. Delbruck, S.C. Liu, R. Douglas, P. Hafliger, G. Jimenez-Moreno, A.C. Ballcels, T. Serrano-Gotarredona, A.J. Acosta-Jimenez, B. Linares-Barranco, "CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing-Learning-Actuating System for High-Speed Visual Object Recognition and Tracking," IEEE Trans. Neural Networks, vol. 20, no. 9, pp. 1417-1438, 2009.
2. R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, C. Serrano-Gotarredona, J.A. Perez-Carrasco, B. Linares-Barranco, A. Linares-Barranco, G. Jimenez-Moreno, and A. Civit-Ballcels, "On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing," IEEE Trans. Neural Networks, vol. 19, no. 7, pg. 1196-1219, 2008.
3. D. Badoni, M. Giulioni, V. Dante, and P. Del Giudice, "An aVLSI recurrent network of spiking neurons with reconfigurable and plastic synapses," Proc. IEEE Int. Symp. Circuits and Systems, pg. 1227-1230, 2006.
4. S. Mitra, S. Fusi, and G. Indiveri, "Real-time classification of complex patterns using spike-based learning in neuromorphic VLSI," IEEE Trans. of Biomedical Circuits and Systems, vol. 3, no. 1, pg. 32-42, Jan. 2009.
5. J. Park, T. Yu, C. Maier, S. Joshi, and G. Cauwenberghs, "Hierarchical address-event routing architecture for reconfigurable large scale neuromorphic systems, Proc. IEEE Int. Symp. Circuits and Systems, 2012, (to appear).
6. T. Yu, J. Park, S. Joshi, C. Maier, and G. Cauwenberghs, "Event-driven neural integration and synchronicity in analog VLSI, Proc. Int. Conf. IEEE Eng. in Medicine and Biology Society, 2012, (to appear).
7. S. Joshi, S. Deiss, M. Arnold, J. Park, T. Yu, and G. Cauwenberghs, "Scaleable event routing in hierarchical neural array architecture with global synaptic connectivity, 12th Intl. Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), 2010, pg. 1-6.
8. T. Yu and G. Cauwenberghs. "Log-Domain Time-Multiplexed Realization of Dynamical Conductance-Based Synapses," Proc. IEEE Int. Symp. Circuits and Systems, 2010, pg. 2558-2561.
9. D.H. Goldberg, G. Cauwenberghs and A.G. Andreou, "Probabilistic Synaptic Weighting in a Reconfigurable Network of VLSI Integrate-and-Fire Neurons," IEEE Trans. Neural Netw., vol. 14, no. 6-7, pg. 781-793, Aug. 2001.
10. R.J. Vogelstein, U. Mallik, J.T. Vogelstein, and G. Cauwenberghs, "Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses," IEEE Trans. Neural Netw., vol. 18, no. 1, pp. 253-265, Jan. 2007.
11. E.M. Izhikevich and F.C. Hoppensteadt, "Polysynchronous wavefront computations," Intl. Journal of Bifurcation and Chaos, vol. 19, pg. 1733-1739, 2009.
12. H.P. Wang, D. Spencer, J.M. Fellous, and T.J. Sejnowski, "Synchrony of thalamocortical inputs maximizes cortical reliability," Science, vol. 328, no. 5974, pg. 106-109, Apr. 2010.
13. G. Pratt, "Pulse computation," Ph.D. dissertation, Dept. of Elect. Eng. and Comp. Sci., Mass. Inst. of Tech., Cambridge, MA, 1990.
14. T. Yu, S. Joshi, V. Rangan, and G. Cauwenberghs, "Subthreshold MOS dynamic translinear neural and synaptic conductance, Proc. IEEE/EMBS Conf. Neur. Eng., 2011, pg. 68-71.
15. Fragniere, E.; van Schaik, A.; and Vittoz, E. "Reactive components for pseudo-resistive networks," Electronics Letters, vol. 33, pg. 1913-1914, 1997.
16. Hamilton, T.J.; Jin, C.; van Schaik, A.; and Tapson, J. "An active 2-D silicon cochlea," IEEE Trans. Biomedical Circuits and Systems, vol. 2, no. 1, pg. 30-43, March 2008.