Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Proceedings of the International Joint Conference on Neural Networks

Volumn , Issue , 2012, Pages

  Arthur, John V ^a   Merolla, Paul A ^a   Akopyan, Filipp ^a   Alvarez, Rodrigo ^a   Cassidy, Andrew ^a   Chandra, Shyamal ^a   Esser, Steven K ^a   Imam, Nabil ^b   Risk, William ^a   Rubin, Daniel B D ^a   Manohar, Rajit ^b   Modha, Dharmendra S ^a  

^a IBM ALMADEN RESEARCH CENTER   (United States)

^b Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTO-ASSOCIATIVE MEMORY; BIOLOGICAL NEURAL SYSTEMS; BRAIN-INSPIRED; BUILDING BLOCKES; COMPACT SIZE; CROSS-BAR MEMORIES; DIGIT RECOGNITION; DIGITAL IMPLEMENTATION; GRAND CHALLENGE; INTEGRATE-AND-FIRE NEURONS; NEUROMORPHIC; NEURON PARAMETERS; PROGRAMMING MODELS; REAL-TIME APPLICATION; SOFTWARE FUNCTIONS; SOFTWARE SIMULATION; TEST CASE; ULTRA-LOW POWER CONSUMPTION;

COMPUTER PROGRAMMING; NEURAL NETWORKS; STATIC RANDOM ACCESS STORAGE; VIRTUAL REALITY;

COMPUTER VISION;

EID: 84865106364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2012.6252637     Document Type: Conference Paper

References (23)

1. C. Mead, Analog VLSI and neural systems. Addison-Wesley, 1989.
2. K. Boahen, "Neurogrid: emulating a million neurons in the cortex," in IEEE international conference of the engineering in medicine and biology society, 2006.
3. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity," IEEE Transactions on Neural Networks, vol. 17, no. 1, pp. 211-221, 2006.
4. A. Montalvo, R. Gyurcsik, and J. Paulos, "Building blocks for a temperature-compensated analog vlsi neural network with on-chip learning," in IEEE International Symposium on Circuits and Systems (ISCAS), vol. 6, 1994, pp. 363-366.
5. R. Ananthanarayanan, S. Esser, H. Simon, and D. Modha, "The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses," in Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis. ACM, 2009, p. 63.
6. B. Shi, E. Tsang, S. Lam, and Y. Meng, "Expandable hardware for computing cortical feature maps," in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2006.
7. J. M. Nageswaran, N. Dutt, J. L. Krichmar, A. Nicolau, and A. Veidenbaum, "Efficient simulation of large-scale spiking neural networks using cuda graphics processors," in Proceedings of the International Joint Conference on Neural Networks (IJCNN). IEEE, 2009, pp. 3201-3208.
8. L. Maguire, T. McGinnity, B. Glackin, A. Ghani, A. Belatreche, and J. Harkin, "Challenges for large-scale implementations of spiking neural networks on FPGAs," Neurocomputing, vol. 71, no. 1-3, 2007.
9. P. Merolla, J. Arthur, F. Akopyan, N. Imam, R. Manohar, and D. Modha, "A digital neurosynaptic core using embedded crossbar memory with 45pj per spike in 45nm," in Custom Integrated Circuits Conference (CICC), 2011 IEEE, sept. 2011, pp. 1 -4.
10. N. Imam and R. Manohar, "Address-event communication using tokenring mutual exclusion," Proceedings of the IEEE International Symposium on Asynchronous Circuits, 2011.
11. R. Manohar, "A case for asynchronous computer architecture," Proceedings of the ISCA Workshop on Complexity-Effective Design, 2000.
12. A. Borst, M. Egelhaaf, and J. Haag, "Mechanisms of dendritic integration underlying gain control in fly motionsensitive interneurons," Journal of Computational Neuroscience, vol. 2, pp. 5-18, 1995, 10.1007/BF00962705. [Online]. Available: http://dx.doi.org/10.1007/BF00962705
13. S. Shalev-shwartz and Y. Singer, "A new perspective on an old perceptron algorithm," in Computational Learning Theory, 2005, pp. 264-278.
14. Y. LeCun and C. Cortes. The MNIST Database of Handwritten Digits. [Online]. Available: http://yann.lecun.com/exdb/mnist/
15. G. Hinton and R. Salakhutdinov, "Reducing the dimensionality of data with neural networks," Science, vol. 313, no. 5786, p. 504, 2006.
16. P. Merolla, T. Ursell, and J. Arthur, "The thermodynamic temperature of a rhythmic spiking network," CoRR, vol. abs/1009.5473, 2010.
17. J. Hopfield, "Neural networks and physical systems with emergent collective computational abilities," Proceedings of the National Academy of Science, vol. 79, 1982.
18. G. Palm, F. Schwenker, and F. Sommer, "Neural associative memories," Biological Cybernetics, vol. 36, 1993.
19. S. Esser, A. Ndirango, and D. Modha, "Binding sparse spatiotemporal patterns in spiking computation," in International Joint Conference on Neural Networks (IJCNN). IEEE, 2010, pp. 1-9.
20. A. Davison, D. Brüderle, J. Eppler, J. Kremkow, E. Muller, D. Pecevski, L. Perrinet, and P. Yger, "PyNN: a common interface for neuronal network simulators," Frontiers in neuroinformatics, vol. 2, 2008.
21. X. Jin, F. Galluppi, C. Patterson, A. Rast, S. Davies, S. Temple, and S. Furber, "Algorithm and software for simulation of spiking neural networks on the multi-chip spinnaker system," in International Joint Conference on Neural Networks (IJCNN). IEEE, 2010, pp. 1-8.
22. J. Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha, and D. Friedman, "A 45nm cmos neuromorphic chip with a scalable architecture for learning in networks of spiking neurons," in Custom Integrated Circuits Conference (CICC), 2011 IEEE, sept. 2011, pp. 1 -4.
23. J. Arthur and K. Boahen, "Recurrently connected silicon neurons with active dendrites for one-shot learning," Neural Networks, Proceedings, vol. 3, pp. 1699 - 1704, 2004.