A multichip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 5, 2007, Pages 981-993

  Chicca, Elisabetta ^a,c   Whatley, Adrian M ^a,c   Lichtsteiner, Patrick ^a,c   Dante, Vittorio ^b   Delbruck, Tobias ^a,c   Del Giudice, Paolo ^b,d   Douglas, Rodney J ^a,c   Indiveri, Giacomo ^a,c  

^a Institute of Neuroinformatics Zurich   (Switzerland)

^b ISTITUTO SUPERIORE DI SANITÀ   (Italy)

^c ETH ZURICH   (Switzerland)

^d INFN SEZIONE DI ROMA   (Italy)

Author keywords

Address event representation (AER); Asynchronous; Cooperative competitive; Neural chips; Neural networks; Neuromorphic; Orientation tuning; Peripheral component interconnect (PCI) AER; VLSI; Winner take all (WTA)

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; NEURAL NETWORKS; TUNING; VLSI CIRCUITS;

ADDRESS EVENT REPRESENTATION (AER); NEURAL CHIPS; NEUROMORPHIC; ORIENTATION TUNING; PERIPHERAL COMPONENT INTERCONNECT (PCI);

MICROPROCESSOR CHIPS;

EID: 34248635722     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.893509     Document Type: Article

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