Reducing latency overhead caused by using LDPC codes in NAND flash memory

Eurasip Journal on Advances in Signal Processing

Volumn 2012, Issue 1, 2012, Pages

  Zhao, Wenzhe ^a   Dong, Guiqiang ^b   Sun, Hongbin ^a   Zheng, Nanning ^a   Zhang, Tong ^c  

^a XI'AN JIAOTONG UNIVERSITY   (China)

^b Skyera Inc   (United States)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Hard decision decoding; LDPC code; NAND flash memory

Indexed keywords

DECODING PERFORMANCE; ERROR CORRECTION CAPABILITY; ERROR CORRECTION CODES; LDPC CODES; LOW-DENSITY PARITY-CHECK (LDPC) CODES; NAND FLASH MEMORY; SEMICONDUCTOR TECHNOLOGY; STORAGE RELIABILITY;

DECODING; DIGITAL STORAGE; FORWARD ERROR CORRECTION; INTEGRATED CIRCUITS; ITERATIVE METHODS; NAND CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE;

COST REDUCTION;

EID: 84887074491     PISSN: 16876172     EISSN: 16876180     Source Type: Journal    
DOI: 10.1186/1687-6180-2012-203     Document Type: Article

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