-
2
-
-
0035246564
-
Factor graphs and the sum-product algorithm
-
Feb
-
F.R. Kschischang, B. J. Frey, and H. A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. Inform. Theory, vol. 47, pp. 498-519, Feb. 2001.
-
(2001)
IEEE Trans. Inform. Theory
, vol.47
, pp. 498-519
-
-
Kschischang, F.R.1
Frey, B.J.2
Loeliger, H.A.3
-
4
-
-
4444270737
-
Memory-efficient sum-product decoding of LDPC codes
-
Aug
-
H. Sankar and K. Narayanan, "Memory-efficient sum-product decoding of LDPC codes," IEEE Trans. Commun., vol. 52, pp. 1225-1230, Aug. 2004.
-
(2004)
IEEE Trans. Commun
, vol.52
, pp. 1225-1230
-
-
Sankar, H.1
Narayanan, K.2
-
5
-
-
0344549794
-
Parallel versus sequential updating for belief propagation decoding
-
Dec
-
H. Kfir and I. Kanter, "Parallel versus sequential updating for belief propagation decoding," Physica A, vol. 330, pp. 259-270, Dec. 2003.
-
(2003)
Physica A
, vol.330
, pp. 259-270
-
-
Kfir, H.1
Kanter, I.2
-
6
-
-
0038304877
-
Shuffled belief propagation decoding
-
Nov
-
J. Zhang and M. P. C. Fossorier, "Shuffled belief propagation decoding," in Proc. Asilomar Conf. on Signals, Systems and Computers vol. 1, pp. 8-15, Nov. 2002.
-
(2002)
Proc. Asilomar Conf. on Signals, Systems and Computers
, vol.1
, pp. 8-15
-
-
Zhang, J.1
Fossorier, M.P.C.2
-
7
-
-
33847660561
-
Optimized message passing schedules for LDPC decoding
-
Nov
-
P. Radosavljevic, A. de Baynast, and J. R. Cavallaro, "Optimized message passing schedules for LDPC decoding," in Proc. Asilomar Conf. on Signals, Systems and Computers, Nov. 2005.
-
(2005)
Proc. Asilomar Conf. on Signals, Systems and Computers
-
-
Radosavljevic, P.1
de Baynast, A.2
Cavallaro, J.R.3
-
8
-
-
0010882063
-
Decoding low-density parity-check codes with probability scheduling
-
Oct
-
Y. Mao and A. H. Banihashemi, "Decoding low-density parity-check codes with probability scheduling," IEEE Commun. Lett., vol. 5, pp. 414-416, Oct. 2001.
-
(2001)
IEEE Commun. Lett
, vol.5
, pp. 414-416
-
-
Mao, Y.1
Banihashemi, A.H.2
-
9
-
-
11844297352
-
Graph-based message-passing schedules for decoding LDPC codes
-
Dec
-
H. Xiao and A. H. Banihashemi, "Graph-based message-passing schedules for decoding LDPC codes," IEEE Trans. Commun., vol. 52, pp. 2098-2105, Dec. 2004.
-
(2004)
IEEE Trans. Commun
, vol.52
, pp. 2098-2105
-
-
Xiao, H.1
Banihashemi, A.H.2
-
10
-
-
11844305971
-
Reliability-based schedule for bitflipping decoding of low-density parity-check codes
-
Dec
-
A. Nouh and A. H. Banishemi, "Reliability-based schedule for bitflipping decoding of low-density parity-check codes," IEEE Trans. Commun., vol. 52, pp. 2038-2040, Dec. 2004.
-
(2004)
IEEE Trans. Commun
, vol.52
, pp. 2038-2040
-
-
Nouh, A.1
Banishemi, A.H.2
-
11
-
-
17444419769
-
An efficient message-passing schedule for LDPC decoding
-
Sept
-
E. Sharon, S. Litsyn, and J. Goldberger, "An efficient message-passing schedule for LDPC decoding," in Proc. Electrical and Electronics Engineer in Israel, pp. 223-226, Sept. 2004.
-
(2004)
Proc. Electrical and Electronics Engineer in Israel
, pp. 223-226
-
-
Sharon, E.1
Litsyn, S.2
Goldberger, J.3
-
12
-
-
33846595264
-
Reduced latency iterative decoding of LDPC codes
-
Dec
-
Y. Wang, J. Zhang, M. Fossorier, and J. S. Yedidia, "Reduced latency iterative decoding of LDPC codes," in Proc. Global Telecomun. Conf. (Globecom), vol. 3, pp. 1199-1204, Dec. 2005.
-
(2005)
Proc. Global Telecomun. Conf. (Globecom)
, vol.3
, pp. 1199-1204
-
-
Wang, Y.1
Zhang, J.2
Fossorier, M.3
Yedidia, J.S.4
-
13
-
-
10644277236
-
LDPC block and convolutional codes based on circulant matrices
-
Dec
-
R. M. Tanner, D. Sridhara, A. Sridharan, T. E. Fuja, and D. J. Costello, "LDPC block and convolutional codes based on circulant matrices," IEEE Trans. Inform. Theory, vol. 50, pp. 2966-2984, Dec. 2004.
-
(2004)
IEEE Trans. Inform. Theory
, vol.50
, pp. 2966-2984
-
-
Tanner, R.M.1
Sridhara, D.2
Sridharan, A.3
Fuja, T.E.4
Costello, D.J.5
-
14
-
-
3042549356
-
Overlapped message passing for quasi-cyclic low density parity check codes
-
June
-
Y. Chen and K. K. Parhi, "Overlapped message passing for quasi-cyclic low density parity check codes," IEEE Trans. Circuits and Systems vol. 51, pp. 1106-1113, June 2004.
-
(2004)
IEEE Trans. Circuits and Systems
, vol.51
, pp. 1106-1113
-
-
Chen, Y.1
Parhi, K.K.2
-
15
-
-
65649103706
-
-
Y. Dai, N. Chen, and Z. Yan, Memory-efficient decoder architectures for quasi-cyclic LDPC codes, accepted and to appear in IEEE Trans. Circuits and Systems.
-
Y. Dai, N. Chen, and Z. Yan, "Memory-efficient decoder architectures for quasi-cyclic LDPC codes," accepted and to appear in IEEE Trans. Circuits and Systems.
-
-
-
-
16
-
-
15744377390
-
A simple convergence comparison of Gallager codes under two message-passing schedules
-
Mar
-
S. Tong and X. Wang, "A simple convergence comparison of Gallager codes under two message-passing schedules," IEEE Commun. Lett., vol. 9, pp. 249-251, Mar. 2005.
-
(2005)
IEEE Commun. Lett
, vol.9
, pp. 249-251
-
-
Tong, S.1
Wang, X.2
-
17
-
-
2442530858
-
Design of low-density parity-check codes for modulation and detection
-
Apr
-
S. ten Brink, G. Kramer, and A. Ashikhmin, "Design of low-density parity-check codes for modulation and detection," IEEE Trans. Commun., vol. 52, pp. 670-678, Apr. 2004.
-
(2004)
IEEE Trans. Commun
, vol.52
, pp. 670-678
-
-
ten Brink, S.1
Kramer, G.2
Ashikhmin, A.3
|