A high-throughput LDPC decoder architecture with rate compatibility

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 4, 2011, Pages 839-847

  Zhang, Kai ^a   Huang, Xinming ^a   Wang, Zhongfeng ^b  

^a Worcester Polytechnic Institute   (United States)

^b BROADCOM CORPORATION   (United States)

Author keywords

LDPC decoder; puncturing scheme; rate compatibility; VLSI design; WiMax

Indexed keywords

ARCHITECTURE; FORWARD ERROR CORRECTION; IEEE STANDARDS; WIMAX;

BER PERFORMANCE; DECODER ARCHITECTURE; LAYERED DECODING; LDPC DECODER; LOW-DENSITY PARITY-CHECK (LDPC) CODES; QUASI-CYCLIC LDPC CODES; RATE COMPATIBILITY; VLSI DESIGN;

DECODING;

EID: 79953282275     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2089551     Document Type: Article

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