Area-efficient min-sum decoder design for high-rate quasi-cyclic low-density parity-check codes in magnetic recording

IEEE Transactions on Magnetics

Volumn 43, Issue 12, 2007, Pages 4117-4122

  Zhong, Hao ^a   Xu, Wei ^b   Xie, Ningde ^b   Zhang, Tong ^b  

^a AGERE SYSTEMS   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Decoder; Low density parity check (LDPC); Min sum algorithm; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DECODING; VLSI CIRCUITS;

DECODERS; LOW-DENSITY PARITY-CHECK (LDPC); MIN-SUM ALGORITHM;

MAGNETIC RECORDING;

EID: 36348998227     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2007.906890     Document Type: Article

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