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Volumn 5, Issue 12, 2013, Pages 5727-5732

In situ synthesis of high density sub-50 nm zno nanopatterned arrays using diblock copolymer templates

Author keywords

atomic layer deposition; block copolymer; flash memory device; nanoarrays; nanolithography; nanoparticle; nanopattern; self assembly; sub 50 nm patterning; ZnO

Indexed keywords

CAPACITANCE VOLTAGE MEASUREMENTS; CHARGE TRAPPING CHARACTERISTICS; DIBLOCK COPOLYMER TEMPLATES; NANO PATTERN; NANOARRAYS; NONVOLATILE MEMORY DEVICES; SUB-50 NM; ZNO;

EID: 84879518072     PISSN: 19448244     EISSN: 19448252     Source Type: Journal    
DOI: 10.1021/am401189p     Document Type: Article
Times cited : (20)

References (47)
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    • Jiang, P.1
  • 10
    • 33644890166 scopus 로고    scopus 로고
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    • (2006) Small , vol.2 , pp. 561-568
    • Fan, H.J.1
  • 16
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    • International Technology Roadmap for Semiconductors, Front End Processes(FEP), 2010 tables.
    • International Technology Roadmap for Semiconductors, Front End Processes(FEP), 2010 tables; http://www.itrs.net/Links/2010ITRS/Home2010.htm.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.