A novel SONOS-type flash device with stacked charge trapping layer

Microelectronic Engineering

Volumn 86, Issue 7-9, 2009, Pages 1863-1865

  Ye, Zong Hao ^a   Chang Liao, Kuei Shu ^a   Liu, Te Chiang ^a   Wang, Tien Ko ^a   Tzeng, Pei Jer ^b   Lin, Cha Hsin ^b   Tsai, Min Jinn ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Bandgap engineering; Charge trapping layer; Flash device

Indexed keywords

BANDGAP ENGINEERING; ELECTRICAL PROPERTY; FLASH DEVICE; FLASH DEVICES; PROGRAM/ERASE; RETENTION CHARACTERISTICS;

ENERGY GAP; HAFNIUM COMPOUNDS; SILICON COMPOUNDS;

CHARGE TRAPPING;

EID: 67349179238     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.03.088     Document Type: Article

References (6)

1. Front-end processing, in: International Technology Roadmap for Semiconductors (ITRS), 2001, p. 41.
2. Shin Y., Choi J., Kang C., Lee C., Park K.-T., Lee J.-S., Sel J., Kim V., Choi B., Sim J., Kim D., Cho H.-j., and Kim K. IEDM Tech. Dig. (2005) 327-330
3. Lue H.-T., Wang S.-Y., Lai E.-K., Shih Y.-H., Lai S.-C., Yang L.-W., Chen K.-C., Ku J., Hsieh K.-Y., Liu R., and Lu C.-Y. IEDM Tech. Dig. 1 (2005) 547-550
4. Sugizaki T., Kohayashi M., Ishidao M., Minakata H., Yamaguchi M., Tamura Y., Sugiyama Y., Nakanishi T., and Tanaka H. Tech. Dig. Symp. VLSI Technol. (2003) 27-28
5. Yan Ny Tan, Wai Kin Chim, Wee Kiong Choi, Moon Sig Joo, Tsu Hau Ng, Byung Jin Cho, IEDM Tech. Dig. (2004) 889-892.
6. Wang Y.Q., Singh P.K., Yoo W.J., Yeo Y.C., Samudra G., Chin A., Hwang W.S., Chen J.H., Wang S.J., and Kwong D.-L. IEDM Tech. Dig. (2005) 162-165