Nanoscale patterning using self-assembled polymers for semiconductor applications

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 19, Issue 6, 2001, Pages 2784-2788

  Guarini, K W ^a   Black, C T ^a   Milkove, K R ^a   Sandstrom, R L ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; BLOCK COPOLYMERS; MOLECULAR WEIGHT; MOS CAPACITORS; NANOSTRUCTURED MATERIALS; PHOTOLITHOGRAPHY; REACTIVE ION ETCHING; SELF ASSEMBLY; SILICON WAFERS; SUBSTRATES; SURFACE TREATMENT; THIN FILMS;

FILM THICKNESS; METAL LIFT OFF; NANOSCALE PATTERNING; POLYMER TEMPLATE; SELF ASSEMBLED POLYMERS; SEMICONDUCTOR APPLICATION;

NANOTECHNOLOGY;

EID: 0035519218     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.1421551     Document Type: Article

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