A 320 mW 342 GOPS real-time dynamic object recognition processor for HD 720p video streams

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 1, 2013, Pages 33-45

  Oh, Jinwook ^a   Kim, Gyeonghoon ^a   Park, Junyoung ^a   Hong, Injoon ^a   Lee, Seungjin ^a   Kim, Joo Young ^a,b   Woo, Jeong Ho ^a,c   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b MICROSOFT RESEARCH   (United States)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

dynamic resource management; dynamic voltage and frequency scaling; heterogeneous; low power processor; Multi core processor; object recognition; scale invariant feature transform

Indexed keywords

DYNAMIC RESOURCE MANAGEMENT; DYNAMIC VOLTAGE AND FREQUENCY SCALING; HETEROGENEOUS; LOW POWER PROCESSORS; MULTI-CORE PROCESSOR; SCALE INVARIANT FEATURE TRANSFORMS;

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; ENERGY MANAGEMENT; FEATURE EXTRACTION; LEARNING SYSTEMS; NATURAL RESOURCES MANAGEMENT; OBJECT RECOGNITION; PROGRAM PROCESSORS; RESOURCE ALLOCATION; VIDEO STREAMING;

PIPELINE PROCESSING SYSTEMS;

EID: 84872113314     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2220651     Document Type: Article

References (30)

1. D. G. Lowe, "Distinctive image features from scale-invariant keypoints," Int. J. Computer Vision, vol. 60, no. 2, pp. 91-110, 2004.
2. M. Martinez, A. Collet, and S. S. Srinivasa, "MOPED: A scalable and low latency object recognition and pose estimation system," in Proc. IEEE Int. Conf. Robotics and Automation, May 2010, pp. 2043-2049.
3. S. Agarwala, T. Anderson, A. Hill, M. D. Ales, R. Damodaran, P. Wiley, S. Mullinnix, J. Leach, A. Lell, M. Gill, A. Rajagopal, A. Chachad, M. Agarwala, J. Apostol, M. Krishnan, D. Bui, Q. An, N. S. Nagaraj, T. Wolf, and T. T. Elappuparackal, "A 600-MHz VLIW DSP," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1532-1544, Nov. 2002. (Pubitemid 35432176)
4. C. M. Wittenbrink, E. Kilgariff, and A. Prabhu, "FERMI GF100 GPU architecture," IEEE Micro, vol. 31, no. 2, pp. 50-59, 2011.
5. A. Dehnhardt, M. B. Kulaczewski, L. Friebe, S. Moch, P. Pirsch, H.-J. Stolberg, and C. Reuter, "A multi-core SoC for advanced image and video compression," in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, Mar. 2005, vol. 5, pp. 665-668.
6. S. Kyo, S. Okazaki, T. Koga, and F. Hidano, "100 GOPS in-vehicle vision processor for pre-crash safety systems," in Proc. IEEE Int. Symp. VLSI Circuits, June 2008, pp. 28-29.
7. B. K. Khailany, T.Williams, J. Lin, E. P. Long,M. Rygh, D.W. Tovey, and W. J. Dally, "A programmable 512 GOPS stream processor for signal, omage, and video processing," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 202-213, Jan. 2008.
8. S. Lee, J. Oh, J. Park, M. Kim, and H.-J. Yoo, "A 345 mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 42-51, Jan. 2011.
9. T.-W. Chen, C.-S. Tang, S.-F. Tsai, C.-H. Tsai, S.-Y. Chien, and L.-G. Chen, "Tera-scale performance machine learning SoC (MLSoC) with dual stream processor architecture for multimedia content analysis," IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2321-2329, Nov. 2010.
10. S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. Mattson, and J. D. Owens, "A bandwidth-efficient architecture for media processing," in Proc. ACM/IEEE Int. Symp. Microarchitecture, Nov. 1998, pp. 3-13.
11. B. Flachs, S. Asango, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H.-J. Oh, S. M. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, N. Yano, D. A. Brokenshire, M. Peyravian, V. To, and E. Iwata, "The microarchitecture of the synergistic processor for a cell processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 63-70, Jan. 2006. (Pubitemid 43145963)
12. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80-tile sub-100-WTeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 29-41, Jan. 2008.
13. T. Mori, Y. Ueda, N. Nonogaki, T. Terazawa, M. Sroka, T. Fujita, T. Kodaka, T. Mori,K.Morita, H. Arakida, T.Miura, Y. Okuda, T.Kizu, and Y. Tsuboi, "Apower, performance scalable eight-cores media processor for mobile multimedia applications," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2957-2965, Nov. 2009.
14. A. A. Abbo, R. P. Kleihorst, V. Choudhary, L. Sevat, P. Wielage, S. Mouy, B. Vermeulen, and M. Heijligers, "Xetal-II: A low-power massively-parallel processor for video scene analysis," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 192-201, Jan. 2008.
15. J. Oh, G. Kim, J. Park, I. Hong, S. Lee, and H.-J. Yoo, "A 320 mW 342 GOPS real-time moving object recognition processor for HD 720p video streams," in IEEE ISSCC 2012 Dig. Tech. Papers, 2012, pp. 220-221.
16. D. M. Tullsen, S. J. Eggers, and H. M. Levy, "Simultaneous multithreading: Maxmizing on-chip parallellism," in Proc. IEEE Conf. Computer Architecture, June 1995, pp. 392-403.
17. J.-Y. Kim, J. Park, S. Lee, M. Kim, J. Oh, and H.-J. Yoo, "A 118.4 GB/s multi-casting network-on-chip with hierarchical star-ring combined yopology for real-time object recognition," IEEE J. Solid-State Circuits, vol. 45, no. 7, pp. 1399-1409, July 2010.
18. G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, and M. L. Scott, "Energy-efficient processor design using multiplie clock domains with dynamic voltage and frequency scaling," in Proc. IEEE Int. Symp. High-Performance Computer Architecture, Feb. 2002, pp. 29-40.
19. S. Lee, J. Kwon, J. Oh, J. Park, and H.-J. Yoo, "A 92 mW 76.8 GOPS vector matching processor with parallel Huffman decoder and query re-ordering buffer for real-time object recognition," in Proc. IEEE Asian Solid-State Circuits Conference, Nov. 2010, pp. 1-4.
20. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, "ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix," in Proc. Int. Conf. Field-Programmable Logic Application, 2003, pp. 61-70.
21. P.M. Heysters, G. J. M. Smit, and E. Molenkamp, "Energy-efficiency of MONTIUM reconfigurable tile processor," in Proc Int. Conf. Engineering of Reconfigurable Systems and Algorithm, 2004, pp. 38-44. (Pubitemid 40155482)
22. V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, "PACT XPP-A self-reconfigurable data processing architecture," Int. J. Supercomputing, vol. 26, no. 2, pp. 167-184, 2003.
23. M.-H. Lee, H. Singh, G. Lu, N. Bagherzadeh, and F. J. Kuradahi, "Design and implementation of the MorphoSys reconfigurable computing processor," J. VLSI Signal Processing Systems, vol. 24, pp. 147-164, 2000. (Pubitemid 30588070)
24. A. Motakis, G. Kornaros, and M. Coppola, "Dynamic resource management in modern multicore SoCs by exposing NoC services," in Proc. IEEE Int. Workshop on Reconfigurable Communication-Centric Systems-on-Chip, June 2011, pp. 1-7.
25. W. Kim et al., "System level analysis of fast, per-core DVFS using on-chip switching regulators," in Proc. IEEE Int. Symp. High Performance Computer Architecture, 2008, pp. 123-134.
26. E. Ipek, O. Mutlu, J. F. Martinez, and R. Caruana, "Self-optimizing memory controllers: A reinforcement learning approach," in IEEE Int. Symp. Computer Architecture, June 2008, pp. 39-50.
27. K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal network on chip: Concepts, architecture, and implementations," IEEE Design & Test of Computers, pp. 414-421, Sept.-Oct. 2005. (Pubitemid 41522729)
28. S. Arakawa, Y. Yamaguchi, S. Akui, Y. Fukuda, H. Sumi, H. Hayashi, M. Igarashi, K. Ito, H. Nagano, M. Imai, and N. Asari, "A 512 GOPS fully-programmable digital image processor with full HD 1080p processing capabilities," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 312-313.
29. T. Kurafuji, M. Haraguchi, M. Nakajima, T. Gyoten, T. Nishijima, H. Yamasaki, Y. Imai, M. Ishizaki, T. Kumaki, Y. Okuno, T. Koide, H. J. Mattausch, and K. Arimoto, "A scalable massively parallel processor for real-time image processing," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 334-335.
30. J.-Y. Kim, M. Kim, S. Lee, J. Oh, K. Kim, and H.-J. Yoo, "A 201.4 GOPS 496 mW real-time multi-object recognition processor with bioinspired neural perception engine," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 32-45, Jan. 2010.