A scalable massively parallel processor for real-time image processing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 334-335

  Kurafuji, Takashi ^a   Haraguchi, Masaru ^a   Nakajima, Masami ^a   Gyoten, Takayuki ^a   Nishijima, Tetsu ^a   Yamasaki, Hiroyuki ^a   Imai, Yuta ^b   Ishizaki, Masakatsu ^a   Kumaki, Takeshi ^b   Okuno, Yoshihiro ^a   Koide, Tetsushi ^b   Jürgen Mattausch, Hans ^b   Arimoto, Kazutami ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM COMPLEXITY; AREA EFFICIENCY; BATTERY LIFE; FRAME RATE; HIGH-POWER; HIGHER RESOLUTION; IMAGE PROCESSORS; LOWER COST; MASSIVELY PARALLEL PROCESSORS; MATRIX PROCESSOR; OPERATING FREQUENCY; PIPELINED ARCHITECTURE; PROCESSING ELEMENTS; PROCESSING PERFORMANCE; REAL-TIME IMAGE PROCESSING; REAL-TIME IMAGES; SILICON AREA; SMARTPHONES; SURVEILLANCE CAMERAS;

IMAGE PROCESSING; NANOTECHNOLOGY; SECURITY SYSTEMS;

REAL TIME SYSTEMS;

EID: 77952179525     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433910     Document Type: Conference Paper

References (6)

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