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Volumn 43, Issue 1, 2008, Pages 192-201

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Author keywords

Low power; parallel processing; processor tile; single instruction multiple data (SIMD); smart cameras; very large scale integration (VLSI); video scene analysis

Indexed keywords


EID: 85008043136     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.909328     Document Type: Article
Times cited : (67)

References (11)
  • 2
    • 3042535216 scopus 로고    scopus 로고
    • Distinctive image features from scale-invariant keypoints
    • Nov.
    • D. Lowe, “Distinctive image features from scale-invariant keypoints,” Int. J. Comput. Vis., vol. 60, no. 2, pp. 91–110, Nov. 2004.
    • (2004) Int. J. Comput. Vis. , vol.60 , Issue.2 , pp. 91-110
    • Lowe, D.1
  • 3
    • 84877215437 scopus 로고
    • Why linear arrays are better image processors
    • P. Jonker, “Why linear arrays are better image processors,” in Proc. 12th IAPR Conf. Pattern Recognition, 1994, pp. 334–338.
    • (1994) Proc. 12th IAPR Conf. Pattern Recognition , pp. 334-338
    • Jonker, P.1
  • 4
    • 0035271572 scopus 로고    scopus 로고
    • Imagine: Media processing with streams
    • Mar./Apr.
    • B. Khailany et al., “Imagine: Media processing with streams,” IEEE Micro, vol. 21, no. 2, pp. 35–46, Mar./Apr. 2001.
    • (2001) IEEE Micro , vol.21 , Issue.2 , pp. 35-46
    • Khailany, B.1
  • 5
    • 85008056349 scopus 로고    scopus 로고
    • Cell.
    • [Online]. Available:
    • Cell. [Online]. Available: http://researchweb.watson.ibm.com
  • 7
    • 27644599162 scopus 로고    scopus 로고
    • An integrated memory array processor for embedded image recognition systems
    • S. Kyo, T. Koga, S. Okazaki, and I. Kuroda, “An integrated memory array processor for embedded image recognition systems,” in Proc. ISCAS, 2005, pp. 134–145.
    • (2005) Proc. ISCAS , pp. 134-145
    • Kyo, S.1    Koga, T.2    Okazaki, S.3    Kuroda, I.4
  • 8
    • 33845585014 scopus 로고    scopus 로고
    • A 40 GOPS 250 mw massively parallel processor based on matrix architecture
    • M. Nakajima et al., “A 40 GOPS 250 mw massively parallel processor based on matrix architecture,” in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 410–411.
    • (2006) IEEE ISSCC Dig. Tech. Papers , pp. 410-411
    • Nakajima, M.1
  • 9
    • 77957346888 scopus 로고    scopus 로고
    • A programmable smart-camera architecture
    • Gent, Belgium, Sep.
    • A. Abbo and R. Kleihorst, “A programmable smart-camera architecture,” in Proc. ACIVS2002, Gent, Belgium, Sep. 2002, pp. 6–13.
    • (2002) Proc. ACIVS2002 , pp. 6-13
    • Abbo, A.1    Kleihorst, R.2
  • 10
    • 0036446081 scopus 로고    scopus 로고
    • Core-based scan architecture for silicon debug
    • Washington, DC
    • B. Vermeulen, T. Waayers, and S. K. Goel, “Core-based scan architecture for silicon debug,” in Proc. IEEE Int. Test Conf., Washington, DC, 2002, p. 638.
    • (2002) Proc. IEEE Int. Test Conf. , pp. 638
    • Vermeulen, B.1    Waayers, T.2    Goel, S.K.3
  • 11
    • 35048895450 scopus 로고    scopus 로고
    • Power consumption of performance-scaled SIMD processors
    • Sep.
    • A. Abbo, R. Kleihorst, V. Choudhary, and L. Sevat, “Power consumption of performance-scaled SIMD processors,” in Proc. PATMOS, Sep. 2004, pp. 532–540.
    • (2004) Proc. PATMOS , pp. 532-540
    • Abbo, A.1    Kleihorst, R.2    Choudhary, V.3    Sevat, L.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.