A 345 mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 42-51

  Lee, Seungjin ^a   Oh, Jinwook ^a   Park, Junyoung ^a   Kwon, Joonsoo ^a   Kim, Minsu ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Multi core processor; network on chip; neuro fuzzy logic; object recognition; visual attention

Indexed keywords

AVERAGE POWER; BACKGROUND REGION; CLUTTERED SCENES; FEATURE MATCHING; INPUT IMAGE; MANY-CORE; MIXED MODE; MULTI-CORE PROCESSOR; NETWORK ON CHIP; NEURO-FUZZY INFERENCE SYSTEMS; NEURO-FUZZY LOGIC; OBJECT REGION; ON-LINE ADAPTATION; PROCESSING ELEMENTS; REAL TIME VIDEOS; ROBUST OBJECT RECOGNITION; SCALE INVARIANT FEATURE TRANSFORMS; TOPDOWN; VECTOR PROCESSING; VISUAL ATTENTION; VISUAL ATTENTION MODEL; WEIGHT PERTURBATION;

FEATURE EXTRACTION; FUZZY INFERENCE; FUZZY SYSTEMS; IMAGE SEGMENTATION; MICROPROCESSOR CHIPS; SERVERS; VLSI CIRCUITS;

OBJECT RECOGNITION;

EID: 78650886575     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2075430     Document Type: Conference Paper

References (18)

1. D. Wagner, G. Reitmayr, A. Mulloni, T. Drummond, and D. Schmalstieg, "Real-time detection and tracking for augmented reality on mobile phones," IEEE Trans. Visual Comput. Graph., vol. 16, no. 3, pp. 355-368, 2010.
2. D. G. Lowe, "Distinctive image features from scale-invariant keypoints," Intl. J. Comp. Vis., vol. 60, no. 2, pp. 91-110, 2004.
3. B. K. Khailany et al., "A programmable 512 GOPS stream processor for signal, image, and video processing," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 202-213, Jan. 2008.
4. S. Arakawa et al., "A 512 GOPS fully-programmable digital image processor with full HD 1080p processing capabilities," in Proc. IEEE ISSCC 2008 Dig. Tech. Papers, pp. 312-313.
5. D. Kim et al., "An 81.6 GOPS object recognition processor based on NoC and visual image processing memory," in Proc. of IEEE CICC, 2007, pp. 443-446.
6. K. Kim et al., "A 125 GOPS 583 mW network-on-chip based parallel processor with bio-inspired visual attention engine," IEEE J. Solid- State Circuits, vol. 44, no. 1, pp. 136-147, Jan. 2009.
7. J.-Y. Kim et al., "A 201.4 GOPS 496mWreal-time multi-object recognition processor with bio-inspired neural perception engine," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 32-45, Jan. 2010.
8. L. Itti, C.Koch, and E. Niebur, "A model of saliency-based visual attention for rapid scene analysis," IEEE Trans. Pattern Anal. Mach. Intell., vol. 20, no. 11, pp. 124-1259, Nov. 1998.
9. S. Lee et al., "The brain mimicking visual attention engine: An 80×60 digital cellular neural network for rapid global feature extraction," in Proc. 2008 Symp. VLSI Circuits Dig. Tech. Papers, pp. 26-27.
10. M. Kim et al., "A 22.8 GOPS 2.83 mW neuro-fuzzy object detection engine for fast multi-object recognition," in Proc. 2009 Symp. VLSI Circuits Dig. Tech. Papers, pp. 260-261.
11. S. Lee et al., "Familiarity based unified visual attention model for fast and robust object recognition," Pattern Recognition, vol. 43, pp. 1116-1128, 2010.
12. S. Lee et al., "A 345 mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition," in Proc. IEEE ISSCC 2010 Dig. Tech. Papers, pp. 332-333.
13. J. Oh et al., "A 1.2 mW on-line learning mixed mode intelligent inference engine for robust object recognition," in Proc. 2010 Symp. VLSI Circuits, 2010, pp. 17-18.
14. J.-S. R. Jang, "ANFIS: Adaptive-network-based fuzzy inference system," IEEE Trans. Syst., Man, Cybern., vol. 23, no. 3, pp. 65-685, Mar. 1993.
15. C. Koch and S. Ullman, "Shifts in selective visual attention: Towards the underlying neural circuitry," Human Neurobiol., vol. 4, pp. 219-297, 916, 1985.
16. J.-Y. Kim et al., "A 118.4 GB/s multi-casting network-on-chip for realtime object recognition processor," in Proc. IEEE ESSCIRC, 2009, pp. 400-403.
17. M. Jabri, "Weight perturbation: An optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks," Neural Comput., vol. 3, no. 4, pp. 546-565, 1991.
18. T. Sakurai, "Alpha-power law MOSFET model and its applications to CMOSinverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, 1990.