Design and implementation of the MorphoSys reconfigurable computing processor

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 24, Issue 2, 2000, Pages 147-164

  Lee, Ming Hau ^a,c   Singh, Hartej ^a,d   Lu, Guangming ^a,e,f   Bagherzadeh, Nader ^a,g,h   Kurdahi, Fadi J ^a,i,j   Filho, Eliseu M C ^b   Alves, Vladimir Castro ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b FEDERAL UNIVERSITY OF RIO DE JANEIRO   (Brazil)

^c NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^d THAPAR UNIVERSITY   (India)

^e TSINGHUA UNIVERSITY   (China)

^f PEKING UNIVERSITY   (China)

^g UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^h LUCENT TECHNOLOGIES   (United States)

ⁱ AMERICAN UNIVERSITY OF BEIRUT   (Lebanon)

^j UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEMS PROGRAMMING; DATA STORAGE EQUIPMENT; INTERFACES (COMPUTER); MATHEMATICAL MODELS; REDUCED INSTRUCTION SET COMPUTING; RESPONSE TIME (COMPUTER SYSTEMS);

RECONFIGURABLE PROCESSING SYSTEMS;

PARALLEL PROCESSING SYSTEMS;

EID: 0033906636     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008189221436     Document Type: Article

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