Tera-scale performance machine learning SoC (MLSoC) with dual stream processor architecture for multimedia content analysis

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 11, 2010, Pages 2321-2329

  Chen, Tse Wei ^a   Tang, Chi Sun ^a   Tsai, Sung Fang ^a   Tsai, Chen Han ^a   Chien, Shao Yi ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Digital circuit; hardware architecture; machine learning; multimedia content analysis; system on a Chip (SoC)

Indexed keywords

AREA EFFICIENCY; CMOS TECHNOLOGY; HARDWARE ARCHITECTURE; HIGH BANDWIDTH; IMAGE STREAMS; MACHINE LEARNING; MACHINE LEARNING ALGORITHMS; MASSIVELY PARALLEL PROCESSING; MULTIMEDIA CONTENT ANALYSIS; POWER EFFICIENCY; STREAM PROCESSOR; SYSTEM-ON-A-CHIP; TWO-STREAM; VLSI ARCHITECTURES; WINDOW-BASED;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER VISION; DIGITAL INTEGRATED CIRCUITS; HYDRAULICS; LEARNING SYSTEMS; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

LEARNING ALGORITHMS;

EID: 77958528530     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2067910     Document Type: Conference Paper

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