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Volumn 44, Issue 11, 2009, Pages 2957-2965

A power, performance scalable eight-cores media processor for mobile multimedia applications

Author keywords

AAC audio decoder; H.264 video decoder; Low power consumption; Mobile multimedia applications; Multi core processor; Scalable performance; Supply voltage control

Indexed keywords

AAC AUDIO DECODER; H.264 VIDEO DECODER; LOW POWER CONSUMPTION; MOBILE MULTIMEDIA APPLICATIONS; MULTI-CORE PROCESSOR; SCALABLE PERFORMANCE; SUPPLY VOLTAGE CONTROL;

EID: 70449504758     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2028936     Document Type: Article
Times cited : (18)

References (9)
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    • T. Shiota et al., A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors, in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 194-195.
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  • 6
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    • M. Ito et al., An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler, in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 90-91.
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  • 7
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    • S. Nomura et al., A.9.7 mW AAC-decoding, 620 mW H.264 720p 60 fps decoding, 8-core media processor with embedded forward-bodybiasing and power gating circuit in 65 nm CMOS technology, IEEE ISSCC Dig. Tech. Papers, pp. 262-263, Feb. 2008.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.