The microarchitecture of the synergistic processor for a cell processor

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 63-70

  Flachs, B ^a   Asano, S ^a   Dhong, Sh ^a   Hofstee, H P ^a   Gervais, G ^a   Kim, Roy ^a   Le, T ^a   Liu, Peichun ^a   Leenstra, J ^a   Liberty, J ^a   Michael, B ^a   Oh, Hwa Joon ^a   Mueller, S M ^a   Takahashi, O ^a   Hatakeyama, A ^a   Watanabe, Y ^a   Yano, N ^a   Brokenshire, D A ^a   Peyravian, M ^a   To, Vandung ^a   Iwata, E ^a   more..

^a IBM   (United States)

Author keywords

11 FO4 streaming data processor; 90 nm; Cell processor; Fine grain clock control; Four way SIMD processor; Instruction latency; Software controls; SOI low k process; Synergistic processor microarchitecture

Indexed keywords

COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; LOGIC DESIGN; MICROCOMPUTERS; SYSTEMS ANALYSIS;

11 FO4 STREAMING DATA PROCESSOR; 90 NM; CELL PROCESSOR; FINE GRAIN CLOCK CONTROL; FOUR WAY SIMD PROCESSOR; INSTRUCTION LATENCY; SOFTWARE CONTROLS; SOI LOW K PROCESS; SYNERGISTIC PROCESSOR MICROARCHITECTURE;

DATA PROCESSING;

EID: 31344445939     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.859332     Document Type: Article

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