-
1
-
-
4644295630
-
Evaluating the Imagine stream architecture
-
Munich, Germany, Jun.
-
J. H. Ahn, W. J. Dally, B. Khailany, U. J. Kapasi, and A. Das, “Evaluating the Imagine stream architecture,” in Proc. 31st Annu. Int. Symp. Computer Architecture, Munich, Germany, Jun. 2004, pp. 14–25.
-
(2004)
Proc. 31st Annu. Int. Symp. Computer Architecture
, pp. 14-25
-
-
Ahn, J.H.1
Dally, W.J.2
Khailany, B.3
Kapasi, U.J.4
Das, A.5
-
2
-
-
85008028888
-
AVC Fidelity Range Extensions Reference Software
-
ISO/IEC 14496-5:2001/Amd 8:2006. [Online]. Available:
-
AVC Fidelity Range Extensions Reference Software. ISO/IEC 14496-5:2001/Amd 8:2006. [Online]. Available: http://www.iso.org
-
-
-
-
3
-
-
0033717865
-
Clock rate versus IPC: The end of the road for conventional microarchitectures
-
V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger, “Clock rate versus IPC: The end of the road for conventional microarchitectures,” in Proc. 27th Annu. Int. Symp. Computer Architecture, 2000, pp. 248–259.
-
(2000)
Proc. 27th Annu. Int. Symp. Computer Architecture
, pp. 248-259
-
-
Agarwal, V.1
Hrishikesh, M.S.2
Keckler, S.W.3
Burger, D.4
-
4
-
-
85008025386
-
Stream processors: Programmability with efficiency
-
Mar.
-
W. J. Dally, U. J. Kapasi, B. Khailany, J. H. Ahn, and A. Das, “Stream processors: Programmability with efficiency,” ACM Queue, vol. 2, no. 1, pp. 52–62, Mar. 2004.
-
(2004)
ACM Queue
, vol.2
, Issue.1
, pp. 52-62
-
-
Dally, W.J.1
Kapasi, U.J.2
Khailany, B.3
Ahn, J.H.4
Das, A.5
-
5
-
-
31344445939
-
The microarchitecture of the synergistic processor for a cell processor
-
Jan.
-
B. Flachs, S. Asango, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H.-J. Oh, S. M. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, N. Yano, D. A. Brokenshire, M. Peyravian, V. To, and E. Iwata, “The microarchitecture of the synergistic processor for a cell processor,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 63–70, Jan. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.1
, pp. 63-70
-
-
Flachs, B.1
Asango, S.2
Dhong, S.H.3
Hofstee, H.P.4
Gervais, G.5
Kim, R.6
Le, T.7
Liu, P.8
Leenstra, J.9
Liberty, J.10
Michael, B.11
Oh, H.-J.12
Mueller, S.M.13
Takahashi, O.14
Hatakeyama, A.15
Watanabe, Y.16
Yano, N.17
Brokenshire, D.A.18
Peyravian, M.19
To, V.20
Iwata, E.21
more..
-
6
-
-
2342652812
-
Stream register files with indexed access
-
Madrid, Spain, Feb.
-
N. Jayasena, M. Erez, J. H. Ahn, and W. J. Dally, “Stream register files with indexed access,” in Proc. 10th Int. Symp. High Performance Computer Architecture, Madrid, Spain, Feb. 2004, pp. 60–72.
-
(2004)
Proc. 10th Int. Symp. High Performance Computer Architecture
, pp. 60-72
-
-
Jayasena, N.1
Erez, M.2
Ahn, J.H.3
Dally, W.J.4
-
7
-
-
84955473128
-
Exploring the VLSI scalability of stream processors
-
Anaheim, CA, Feb.
-
B. Khailany, W. J. Dally, S. Rixner, U. J. Kapasi, J. D. Owens, and B. Towles, “Exploring the VLSI scalability of stream processors,” in Proc. 9th Int. Symp. High Performance Computer Architecture, Anaheim, CA, Feb. 2003, pp. 153–164.
-
(2003)
Proc. 9th Int. Symp. High Performance Computer Architecture
, pp. 153-164
-
-
Khailany, B.1
Dally, W.J.2
Rixner, S.3
Kapasi, U.J.4
Owens, J.D.5
Towles, B.6
-
8
-
-
34548833277
-
A programmable 512 GOPS stream processor for signal, image, and video processing
-
B. Khailany, T. Williams, J. Lin, E. Long, M. Rygh, D. Tovey, and W. J. Dally, “A programmable 512 GOPS stream processor for signal, image, and video processing,” in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 272–273.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 272-273
-
-
Khailany, B.1
Williams, T.2
Lin, J.3
Long, E.4
Rygh, M.5
Tovey, D.6
Dally, W.J.7
-
9
-
-
35348861326
-
Comparing memory systems for chip multiprocessors
-
San Diego, CA, Jun.
-
J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, and C. Kozyrakis, “Comparing memory systems for chip multiprocessors,” in Proc. 34th Int. Symp. Computer Architecture, San Diego, CA, Jun. 2007, pp. 358–368.
-
(2007)
Proc. 34th Int. Symp. Computer Architecture
, pp. 358-368
-
-
Leverich, J.1
Arakida, H.2
Solomatnikov, A.3
Firoozshahian, A.4
Horowitz, M.5
Kozyrakis, C.6
-
10
-
-
0033688597
-
Smart memories: A modular reconfigurable architecture
-
Jun.
-
K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally, and M. Horowitz, “Smart memories: A modular reconfigurable architecture,” in Proc. 27th Annu. Int. Symp. Computer Architecture, Jun. 2000, pp. 161–171.
-
(2000)
Proc. 27th Annu. Int. Symp. Computer Architecture
, pp. 161-171
-
-
Mai, K.1
Paaske, T.2
Jayasena, N.3
Ho, R.4
Dally, W.J.5
Horowitz, M.6
-
11
-
-
78650845314
-
Radeon R600, a 2nd generation unified shader architecture
-
Stanford, CA
-
M. Mantor, “Radeon R600, a 2nd generation unified shader architecture,” presented at the Hot Chips 19 Symp., Stanford, CA, 2007.
-
(2007)
presented at the Hot Chips 19 Symp.
-
-
Mantor, M.1
-
12
-
-
63849197781
-
NVIDIA GPU parallel computing architecture
-
Stanford, CA
-
J. Nickolls, “NVIDIA GPU parallel computing architecture,” presented at the Hot Chips 19 Symp., Stanford, CA, 2007.
-
(2007)
presented at the Hot Chips 19 Symp.
-
-
Nickolls, J.1
-
13
-
-
0032312385
-
A bandwidth-efficient architecture for media processing
-
S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. Mattson, and J. D. Owens, “A bandwidth-efficient architecture for media processing,” in Proc. 31st Annu. Int. Symp. Microarchitecture, 1998, pp. 3–13.
-
(1998)
Proc. 31st Annu. Int. Symp. Microarchitecture
, pp. 3-13
-
-
Rixner, S.1
Dally, W.J.2
Kapasi, U.J.3
Khailany, B.4
Lopez-Lagunas, A.5
Mattson, P.6
Owens, J.D.7
-
14
-
-
0034581535
-
Register organization for media processing
-
Jan.
-
S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, “Register organization for media processing,” in Proc. 6th Int. Symp. High-Performance Computer Architecture, Jan. 2000, pp. 375–386.
-
(2000)
Proc. 6th Int. Symp. High-Performance Computer Architecture
, pp. 375-386
-
-
Rixner, S.1
Dally, W.J.2
Khailany, B.3
Mattson, P.4
Kapasi, U.J.5
Owens, J.D.6
-
15
-
-
84959045524
-
StreamIt: A language for streaming applications
-
Grenoble, France, Apr.
-
W. Thies, M. Karczmarek, and S. Amarasinghe, “StreamIt: A language for streaming applications,” in Proc. Int. Conf. Compiler Construction, Grenoble, France, Apr. 2002, pp. 179–196.
-
(2002)
Proc. Int. Conf. Compiler Construction
, pp. 179-196
-
-
Thies, W.1
Karczmarek, M.2
Amarasinghe, S.3
|