A 512GOPS fully-programmable digital image processor with full HD 1080p processing capabilities

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 312-314

  Arakawa, Sumito ^a   Yamaguchi, Yuji ^a   Akui, Satoshi ^a   Fukuda, Yasushi ^a   Sumi, Hirofumi ^a   Hayashi, Hiroshi ^a   Igarashi, Masahiro ^a   Ito, Kei ^a   Nagano, Hidetoshi ^a   Imai, Masatoshi ^a   Asari, Naosuke ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

65NM CMOS; BODY BIAS; DIGITAL IMAGE; FULLY PROGRAMMABLES; MAXIMUM POWER; PEAK PERFORMANCE; POWER GATINGS; PROCESSING CAPABILITY;

IMAGE PROCESSING;

EID: 49549115553     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523182     Document Type: Conference Paper

References (4)

1. Satoshi Yoshihara, et al., "A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change," IEEE J. Solid-State Circuits, vol. 41, pp. 2998-3006, Dec. 2006.
2. Masami Nakajima, et al., "A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture," ISSCC Dig. Tech. Papers, pp. 410-411, Feb. 2006
3. Brucek Khailany, et al., "A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing," ISSCC Dig. Tech Papers, pp. 272-273, Feb. 2007.
4. A. Abbo, et al., "XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis," ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2007.