A Power-Optimal Design Methodology for High-Resolution Low-Bandwidth SC ΣΔ Modulators

IEEE Transactions on Instrumentation and Measurement

Volumn 61, Issue 11, 2012, Pages 2896-2904

  Porrazzo, Serena ^a   Cannillo, Francesco ^b,c   Van Hoof, Chris ^c   Cantatore, Eugenio ^b   Van Roermund, Arthur H M ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b IMEC   (Belgium)

^c City Semiconductor   (United States)

Author keywords

Analog to Digital Converter (ADC); power optimization; sigma delta modulator; switched capacitor (SC)

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CMOS PROCESSS; DESIGN METHODOLOGY; EXPERIMENTAL PROTOTYPE; FEED-FORWARD TOPOLOGY; HIGH RESOLUTION; LOOP ORDER; LOW-BANDWIDTH; OVER SAMPLING RATIO; POWER EFFICIENT; POWER OPTIMIZATION; QUANTIZERS; SAMPLING RATES; SIGMA DELTA MODULATOR; SIGNAL BANDWIDTH; SWITCHED CAPACITOR;

CAPACITORS; CMOS INTEGRATED CIRCUITS; OPTIMAL SYSTEMS;

MODULATORS;

EID: 84867579821     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2012.2200812     Document Type: Article

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