A Design Approach for Power-Optimized Fully Reconfigurable AE A/D Converter for 4G Radios

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 3, 2008, Pages 229-233

  Ke, Yi ^a   Gielen, Georges ^a   Craninckx, Jan ^b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

Author keywords

4G radios; analog digital converter (ADC); continuous time (CT); delta sigma modulator (DSM); design approach; power optimization; reconfigurable

Indexed keywords

CONTINUOUS TIME SYSTEMS; DELTA SIGMA MODULATION; OPTIMIZATION; RADIO; TOPOLOGY;

DESIGN APPROACH; FILTER ORDER; OVERSAMPLING RATIOS; POWER OPTIMIZATION; QUANTIZER BITS;

ANALOG TO DIGITAL CONVERSION;

EID: 42149093092     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.918974     Document Type: Article

References (12)

1. R. H. M. van Veldhoven, “A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2K/UMTS receiver,” IEEE J. Solid State Circuits, vol. 38, no. 12, pp. 2069–2076, Dec. 2003.
2. J. Arias, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J. S. Pablo, L. Quintanilla, and J. Barbolla, “A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multimode wire-less-LAN receivers,” IEEE J. Solid State Circuits, vol. 41, no. 2, pp. 339–351, Feb. 2006.
3. S. Ouzounov, R. van Veldhoven, C. Bastiaansen, K. Vongehr, R. van Wegberg, G. Geelen, L. Breems, and A. van Roermund, “A 1.2v 121-mode CT ΔΣ modulator for wireless receivers in 90-nm CMOS,” in Dig. Tech Papers ISSCC, Feb. 2007, pp. 238–239.
4. R. Schreier, “The Delta-Sigma Toolbox Version 7.1,” Mathworks, Natick, MA, Jan. 2000 [Online]. Available: http://mathworks.com/mat-labcentral/fileexchange
5. R. Schreier, “An empirical study of high-order single-bit delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 40, no. 8, pp. 461–466, Aug. 1993.
6. M. Schimper, L. Dorrer, E. Riccio, and G. Panov, “A 3-mW continuous-time AE-modulator for EDGE/GSM with high adjacent channel tolerance,” in Proc. Eur. Solid State Circuits Conf., 2004, pp. 183–186.
7. M. Ortmanns, F. Gerfers, and Y. Manoli, “Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators,” IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 51, no. 6, pp. 1088–1100, Jun. 2004.
8. H. Zhaohui and Z. peixin, “An architectural power estimation for analog-to-digital converters,” Proc. IEEE ICCD, pp. 1063/04-6404/04, 2004.
9. T. Christen, T. Burger, and H. Quiting, “A 0.13 um CMOS EDGE/UMTS/WLAN tri-mode ΔΣ ADC with -92 THD,” in Dig. Tech Papers ISSCC, Feb. 2007, pp. 240–241.
10. m-RC biquadratic cells for Software Defined Radio applications,” Proc. ISCAS, pp. 1047–1050, May 2006.
11. M. Gerhard, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS continuous-time AE ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2461–2469, Dec. 2006.
12. Y. Fujimoto, Y. Kanazawa, P. Lore, and M. Miyamoto, “An 80/100-MHz/s 76.3/70.1-dB SNDR ΔΣ ADC for digital TV receivers,” in Dig. Tech Papers ISSCC, Feb. 2006, pp. 201–210.