Power optimization of high-resolution low-bandwidth SC ΔΣ modulators

IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum

Volumn , Issue , 2011, Pages 126-131

  Porrazzo, Serena ^a   Cannillo, Francesco ^b   Van Hoof, Chris ^b,c   Cantatore, Eugenio ^a   Van Roermund, Arthur H M ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b IMEC   (Belgium)

^c HOLST CENTRE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; EXPERIMENTAL PROTOTYPE; FEED-FORWARD; HIGH RESOLUTION; LOOP ORDER; LOW-BANDWIDTH; OVER SAMPLING RATIO; POWER EFFICIENT; POWER OPTIMIZATION; QUANTIZERS; SAMPLING RATES; SIGNAL BANDWIDTH; SIGNALTONOISE RATIO (SNR); SWITCHED CAPACITOR; TOTAL POWER;

CAPACITORS; CMOS INTEGRATED CIRCUITS;

MODULATORS;

EID: 84872592222     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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