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Volumn , Issue , 2010, Pages 369-372

Power optimization of high performance ΔΣ modulators for portable measurement applications

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; CLASS-AB; CMOS PROCESSS; CURRENT MIRRORS; FIGURE OF MERIT; LOW COSTS; MEASURED RESULTS; MULTI-BITS; POWER EFFICIENT; POWER OPTIMIZATION; POWER SAVINGS; SINGLE-BIT; TOTAL POWER CONSUMPTION; ULTRA-LOW POWER;

EID: 79952840084     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2010.5716632     Document Type: Conference Paper
Times cited : (11)

References (6)
  • 1
    • 8344228535 scopus 로고    scopus 로고
    • A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90- Nm CMOS
    • Nov.
    • Libin Yao, Michiel S. J. Steyaert and Willy Sansen, "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90- nm CMOS", IEEE J. Solid-State Circuits, vol. 39, no. 11, pp.1809-1818, Nov. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.11 , pp. 1809-1818
    • Yao, L.1    Steyaert, M.S.J.2    Sansen, W.3
  • 2
    • 28144445356 scopus 로고    scopus 로고
    • A Low-Power Multi-Bit ΔΣ Modulator in 90nm Digital CMOS without DEM
    • Feb.
    • Jiang Yu and Franco Maloberti, "A Low-Power Multi-Bit ΔΣ Modulator in 90nm Digital CMOS without DEM", ISSCC Dig. Tech. Papers, pp.168-169, Feb. 2005.
    • (2005) ISSCC Dig. Tech. Papers , pp. 168-169
    • Yu, J.1    Maloberti, F.2
  • 5
    • 38849162117 scopus 로고    scopus 로고
    • A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator with 83-dB Dynamic Range
    • Feb.
    • J. Roh, S. Byun, Y. Choi, H. Roh, Y.-G. Kim and J.-K. Kee, "A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator with 83-dB Dynamic Range," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.2 , pp. 361-370
    • Roh, J.1    Byun, S.2    Choi, Y.3    Roh, H.4    Kim, Y.-G.5    Kee, J.-K.6
  • 6
    • 0024737353 scopus 로고
    • A Parasitic-Insensitive Area-Efficient Approach to Realizing Very Large Time Constants in Switched-Capacitor Circuits
    • Sep.
    • K. Nagaraj, "A Parasitic-Insensitive Area-Efficient Approach to Realizing Very Large Time Constants in Switched-Capacitor Circuits," IEEE Trans. Circuit Syst., vol.36, no. 9, pp. 1210-1216, Sep.1989.
    • (1989) IEEE Trans. Circuit Syst. , vol.36 , Issue.9 , pp. 1210-1216
    • Nagaraj, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.