A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2 nd-order ΔΣ ADC for WCDMA in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Koh, Jinseok ^a   Choi, Yunyoung ^a   Gomez, Gabriel ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144463394     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. G. Gomez and B. Haroun, "A 1.5 V 2.4/2.9mW 79/50 dB DR ΔΣ Modulator for GSM/WCDMA in a 0.13μm Digital Process," ISSCC Dig. Tech. Papers, pp242-243, Feb., 2002.
2. D. Senderowicz, et al., "Low-Voltage Double-Sampled ΔΣ Converters," IEEE J. Solid-State Circuits, vol. 37, pp: 1215-1225, Dec., 1997.
3. J. Koh, "Alternating Gain Error Cancellation technique in Double-sampling Delta-Sigma ADC," Patent pending.
4. J. Koh, "Higher Order Delta-Sigma Analog-to-Digital Convert Based On Finite Impulse Response Filter," Patent pending.
5. B. Leung and S. Sutarja, "Multibit ΔΣ A/D Converter Incorporating a Novel Class of Dynamic Element Matching Techniques," IEEE T. Circuits and systems II, vol. 39, pp. 35-51, Jan., 1992.