An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Volumn , Issue , 2006, Pages 63-66

  Su, Chauchin ^a   Lin, Po Chen ^a   Lu, Hung Wen ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC POWER UTILIZATION;

CASCODE STRUCTURE; GAIN ENHANCEMENT; OFFSET CANCELATION;

ANALOG TO DIGITAL CONVERSION;

EID: 34250876943     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357852     Document Type: Conference Paper

References (9)

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3. Marques, A; V. Peluso, M.S. Steyaert, W.M. Sansen, "Optimal parameters for △Σ modulator topologies," IEEE Trans. On Circuits and Systems II; Analog and Digital Signal Processing, Vol 45-9, 1998, pp. 1232-1241.
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7. Li, Q.Y.; J. Van der Spiegel, K.R. Laker, "A 1.2 V, 38 μW second-order △Σ modulator with signal adaptive control architecture," Low Power/Low Voltage Mixed-Signal Circuits and Systems, 2001. (DCAS-01). Proceedings of the IEEE 2nd Dallas CAS Workshop, March 2001, pp. 23-26.
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