Algorithms for gate sizing and device parameter selection for high-performance designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 10, 2012, Pages 1558-1571

  Ozdal, Muhammet Mustafa ^a   Burns, Steven ^a   Hu, Jiang ^b  

^a INTEL CORPORATION   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Circuit optimization; dynamic programming; gate sizing; Lagrangian Relaxation

Indexed keywords

CIRCUIT OPTIMIZATION; DEVICE PARAMETERS; DISCRETE OPTIMIZATION PROBLEMS; GATE SIZING; GRAPH MODEL; GRAPH PROBLEMS; HIGH-PERFORMANCE CIRCUITS; HIGH-PERFORMANCE DESIGN; HIGH-PERFORMANCE MICROPROCESSORS; INDUSTRIAL OPTIMIZATION; LAGRANGIAN; LAGRANGIAN RELAXATION; LEAKAGE POWER REDUCTION; LIBRARY DATA; LOW POWER; PRACTICAL PROBLEMS; SIGN-OFF; STATE OF THE ART; TIMING ANALYSIS;

DESIGN; DYNAMIC PROGRAMMING; GATES (TRANSISTOR); GRAPH THEORY; LAGRANGE MULTIPLIERS; LOW POWER ELECTRONICS; OPTIMIZATION;

ALGORITHMS;

EID: 84866598027     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2196279     Document Type: Article

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