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Volumn 1, Issue , 2005, Pages 381-386

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation

Author keywords

[No Author keywords available]

Indexed keywords

ASSIGNMENT TECHNIQUE; CUSTOM DESIGN; LAGRANGIAN RELAXATION; OPTIMIZATION SOLVERS; POWER OPTIMIZATION; RUNTIME AND MEMORY USAGE;

EID: 84861419836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (42)

References (20)
  • 2
  • 6
    • 0035014649 scopus 로고    scopus 로고
    • Optimal assignment of high threshold vottage for synthesizing dual threshold cmos circuits
    • N. Tripathi, A. Bhosle, D. Samanta, and A. Pal. "Optimal assignment of high threshold vottage for synthesizing dual threshold cmos circuits," in VISI Design. India, 2001, pp. 227-232
    • (2001) VISI Design India , pp. 227-232
    • Tripathi, N.1    Bhosle, A.2    Samanta, D.3    Pal, A.4
  • 7
    • 84861436705 scopus 로고    scopus 로고
    • Total power optimization by simultaneous dual-vt allocation and device sizing in high performance microprocessors
    • T. Karnik, Y. Ye, J. Tschanz. L. Wei, S. Bums, V. Covindarajulu, V. De, and S. Borkar, "Total power optimization by simultaneous dual-vt allocation and device sizing in high performance microprocessors," in IEEHACM DAC, 2002. pp, 48-9 1.
    • (2002) IEEHACM DAC , pp. 48-91
    • Karnik, T.1    Ye, Y.2    Tschanz, J.3    Wei, L.4    Bums, S.5    Covindarajulu, V.6    De, V.7    Borkar, S.8
  • 10
    • 0034228756 scopus 로고    scopus 로고
    • A new class of convex functions for dctay modeling and their application to the transistor sizing problem
    • July
    • K. Kasamsetty, M. Ketkar, and S. S, Sapatnekar. "A new class of convex functions for dctay modeling and their application to the transistor sizing problem," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 19, no. 7, pp. 779-788, July 2000.
    • (2000) IEEE Transactions on Computer-Aided Design of ICs and Systems , vol.19 , Issue.7 , pp. 779-788
    • Kasamsetty, K.1    Ketkar, M.2    Sapatnekar, S.S.3
  • 12
    • 0003997741 scopus 로고    scopus 로고
    • User's guide for cfsqp version 2.4: A e code for solving (large scale) constrained nonlinear (min-max) optimization problems. generating iterates satisfying all inequality constraints
    • Lawrence, C., Zhou. J. L.. Tits, and A. L.. "User's guide for cfsqp version 2.4: A E code for solving (large scale) constrained nonlinear (min-max) optimization problems. generating iterates satisfying all inequality constraints," Institute for Systems Research. University of Maryland, College Park, MD, Tech. Rep. TR-94-16r1, 1996.
    • (1996) Institute for Systems Research. University of Maryland, College Park, MD, Tech. Rep. TR-94-16r1
    • Lawrence, C.1    Zhou, J.L.2    Tits, A.L.3
  • 14
    • 0036911571 scopus 로고    scopus 로고
    • Gate sizing using lagrangian relaxation combined with afutgradient-based preprocessing step
    • H. Tennakoon and C. Sechen, "Gate sizing using lagrangian relaxation combined with afutgradient-based preprocessing step." in ICCAD. 2002. pp. 395-402.
    • (2002) ICCAD , pp. 395-402
    • Tennakoon, H.1    Sechen, C.2
  • 15
    • 0002467356 scopus 로고
    • Global convergence of a class of trust region algorithms for optimization with simple hounds
    • A. R. Conn, N. Could, and P. L. Toint, "Global convergence of a class of trust region algorithms for optimization with simple hounds," SIAM J. Numerical Analysis, vol. 25. pp. 433-460. 1988.
    • (1988) SIAM J. Numerical Analysis , vol.25 , pp. 433-460
    • Conn, A.R.1    Could, N.2    Toint, P.L.3
  • 17
  • 18
    • 0035301566 scopus 로고    scopus 로고
    • Dual-threshold voltage assignment with transistor sizing for low power cmos circuits
    • April
    • P. Pant, R. K. Roy, and A. Chatterjee. "Dual-threshold voltage assignment with transistor sizing for low power cmos circuits," IEEE Transactions VLSI Systems. vol. 9, no. 2, pp. 390-394, April 2001.
    • (2001) IEEE Transactions VLSI Systems , vol.9 , Issue.2 , pp. 390-394
    • Pant, P.1    Roy, R.K.2    Chatterjee, A.3
  • 19
    • 0036907253 scopus 로고    scopus 로고
    • Parameter variations and impacts on circuits and microarchitecture
    • M. Ketkar and S. Sapatnekar, "Parameter variations and impacts on circuits and microarchitecture," in IEEE Conference on Computer-Aided Design, 2002. pp. 375-378.
    • (2002) IEEE Conference on Computer-Aided Design , pp. 375-378
    • Ketkar, M.1    Sapatnekar, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.