-
1
-
-
27944476890
-
-
DAC
-
Agarwal, A., Chopra, K., Blaauw, D., and Zolotov, V.: Circuit optimization using statistical static timing analysis. Proc. DAC (2005), 321-324.
-
(2005)
Circuit optimization using statistical static timing analysis. Proc
, pp. 321-324
-
-
Agarwal, A.1
Chopra, K.2
Blaauw, D.3
Zolotov, V.4
-
2
-
-
3242815471
-
-
Burger, D., Keckler, S.W., McKinley, K.S., Dahlin, M., John, L.K., Lin, C. Moore, C.R., Burrill, J., Mcdonald, R.G., Yoder,W., and the TRIPS team: Scaling to the end of silicon with edge architectures. Computer 37 (7), 2004, 44-55.
-
Burger, D., Keckler, S.W., McKinley, K.S., Dahlin, M., John, L.K., Lin, C. Moore, C.R., Burrill, J., Mcdonald, R.G., Yoder,W., and the TRIPS team: Scaling to the end of silicon with edge architectures. Computer 37 (7), 2004, 44-55.
-
-
-
-
3
-
-
0032685389
-
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
-
Chen, C.-P., Chu, C.C.N., and Wong, D.F.: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on Computer-Aided Design 18 (7), 1999, 1014-1025.
-
(1999)
IEEE Trans. on Computer-Aided Design
, vol.18
, Issue.7
, pp. 1014-1025
-
-
Chen, C.-P.1
Chu, C.C.N.2
Wong, D.F.3
-
4
-
-
0025745782
-
iCOACH: A circuit optimization aid for CMOS high-performance circuits
-
Chen, H.Y., and Kang, S.M.: iCOACH: a circuit optimization aid for CMOS high-performance circuits. Integration, the VLSI Journal 10, 1991, 185-212.
-
(1991)
Integration, the VLSI Journal
, vol.10
, pp. 185-212
-
-
Chen, H.Y.1
Kang, S.M.2
-
5
-
-
26144438998
-
-
Dai, Z.-J., and Asada, K.: MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates. IEEE Custom Integrated Circuits Conference (1989), 17.3.1-17.3.4.
-
Dai, Z.-J., and Asada, K.: MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates. IEEE Custom Integrated Circuits Conference (1989), 17.3.1-17.3.4.
-
-
-
-
6
-
-
0022231945
-
-
Fishburn, J. and Dunlop, A.: TILOS: A posynomial programming approach to transistor sizing. Proc. ICCAD (1985). Digest of Technical Papers, 326-328.
-
Fishburn, J. and Dunlop, A.: TILOS: A posynomial programming approach to transistor sizing. Proc. ICCAD (1985). Digest of Technical Papers, 326-328.
-
-
-
-
7
-
-
33750598417
-
A Unified Theory of Timing Budget Management
-
Ghiasi, S., Bozorgzadeh, E., Huang, P.-K., Jafari, R., and Sarrafzadeh, M.: A Unified Theory of Timing Budget Management. IEEE Trans. on Computer-Aided Design 25 (11), 2006, 2364-2375.
-
(2006)
IEEE Trans. on Computer-Aided Design
, vol.25
, Issue.11
, pp. 2364-2375
-
-
Ghiasi, S.1
Bozorgzadeh, E.2
Huang, P.-K.3
Jafari, R.4
Sarrafzadeh, M.5
-
8
-
-
0025721599
-
Transistor sizing for large combinational digital CMOS circuits
-
Heusler, L.S., and Fichtner, W.: Transistor sizing for large combinational digital CMOS circuits. Integration, the VLSI Journal 10, 1991, 155-168.
-
(1991)
Integration, the VLSI Journal
, vol.10
, pp. 155-168
-
-
Heusler, L.S.1
Fichtner, W.2
-
9
-
-
0019896149
-
Timing Analysis of Computer Hardware
-
Hitchcock, R.B., Smith, G.L., and Cheng, D.D.: Timing Analysis of Computer Hardware. IBM Journal of Research and Development 26 (1), 1982, 100-105.
-
(1982)
IBM Journal of Research and Development
, vol.26
, Issue.1
, pp. 100-105
-
-
Hitchcock, R.B.1
Smith, G.L.2
Cheng, D.D.3
-
11
-
-
41549134131
-
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation
-
Khandelwal, V., and Srivastava, A.: Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. IEEE Trans. on Computer-Aided Design 27, 2008, 610-620.
-
(2008)
IEEE Trans. on Computer-Aided Design
, vol.27
, pp. 610-620
-
-
Khandelwal, V.1
Srivastava, A.2
-
12
-
-
2942640151
-
Transistor Level Budgeting for Power Optimization
-
Kursun, E., Ghiasi, S., and Sarrafzadeh, M. : Transistor Level Budgeting for Power Optimization. Proc. of the 5th International Symp. on Quality Electronic Design (2004), 116-121.
-
(2004)
Proc. of the 5th International Symp. on Quality Electronic Design
, pp. 116-121
-
-
Kursun, E.1
Ghiasi, S.2
Sarrafzadeh, M.3
-
13
-
-
0027701389
-
An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
-
Sapatnekar, S.S., Rao, V.B., Vaidya, P.M., and Kang, S.-M.: An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization. IEEE Trans. on Computer-Aided Design 12 (11), 1993, 1621-1634.
-
(1993)
IEEE Trans. on Computer-Aided Design
, vol.12
, Issue.11
, pp. 1621-1634
-
-
Sapatnekar, S.S.1
Rao, V.B.2
Vaidya, P.M.3
Kang, S.-M.4
-
14
-
-
27944492787
-
-
DAC
-
Singh, J., Nookala, V., Luo, Z.-Q., and Sapatnekar, S.S.: Robust gate sizing by geometric programming. Proc. DAC (2005), 315-320.
-
(2005)
Robust gate sizing by geometric programming. Proc
, pp. 315-320
-
-
Singh, J.1
Nookala, V.2
Luo, Z.-Q.3
Sapatnekar, S.S.4
-
15
-
-
33750594762
-
Statistical Timing Yield Optimization by Gate Sizing
-
Sinha, D., Shenoy, N.V., and Zhou, H.: Statistical Timing Yield Optimization by Gate Sizing. IEEE Transactions on VLSI Systems 14 (10), 2006, 1140-1146.
-
(2006)
IEEE Transactions on VLSI Systems
, vol.14
, Issue.10
, pp. 1140-1146
-
-
Sinha, D.1
Shenoy, N.V.2
Zhou, H.3
-
16
-
-
0036575359
-
Fast and exact transistor sizing based on iterative relaxation
-
Sundararajan, V., Sapatnekar, S.S., and Parhi, K.K.: Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. on Computer-Aided Design 21 (5), 2002, 568 - 581.
-
(2002)
IEEE Trans. on Computer-Aided Design
, vol.21
, Issue.5
, pp. 568-581
-
-
Sundararajan, V.1
Sapatnekar, S.S.2
Parhi, K.K.3
-
17
-
-
50249166712
-
Gate sizing by Lagrangian relaxation revisited. Proc
-
Wang, J., Das, D., and Zhou, H.: Gate sizing by Lagrangian relaxation revisited. Proc. ICCAD (2007), 111-118.
-
(2007)
ICCAD
, pp. 111-118
-
-
Wang, J.1
Das, D.2
Zhou, H.3
|