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Volumn , Issue , 2009, Pages 827-832

Gate sizing for large cell-based designs

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; ITERATIVE METHODS;

EID: 70350070734     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090777     Document Type: Conference Paper
Times cited : (21)

References (17)
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    • Burger, D., Keckler, S.W., McKinley, K.S., Dahlin, M., John, L.K., Lin, C. Moore, C.R., Burrill, J., Mcdonald, R.G., Yoder,W., and the TRIPS team: Scaling to the end of silicon with edge architectures. Computer 37 (7), 2004, 44-55.
  • 3
    • 0032685389 scopus 로고    scopus 로고
    • Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
    • Chen, C.-P., Chu, C.C.N., and Wong, D.F.: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on Computer-Aided Design 18 (7), 1999, 1014-1025.
    • (1999) IEEE Trans. on Computer-Aided Design , vol.18 , Issue.7 , pp. 1014-1025
    • Chen, C.-P.1    Chu, C.C.N.2    Wong, D.F.3
  • 4
    • 0025745782 scopus 로고
    • iCOACH: A circuit optimization aid for CMOS high-performance circuits
    • Chen, H.Y., and Kang, S.M.: iCOACH: a circuit optimization aid for CMOS high-performance circuits. Integration, the VLSI Journal 10, 1991, 185-212.
    • (1991) Integration, the VLSI Journal , vol.10 , pp. 185-212
    • Chen, H.Y.1    Kang, S.M.2
  • 5
    • 26144438998 scopus 로고    scopus 로고
    • Dai, Z.-J., and Asada, K.: MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates. IEEE Custom Integrated Circuits Conference (1989), 17.3.1-17.3.4.
    • Dai, Z.-J., and Asada, K.: MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates. IEEE Custom Integrated Circuits Conference (1989), 17.3.1-17.3.4.
  • 6
    • 0022231945 scopus 로고    scopus 로고
    • Fishburn, J. and Dunlop, A.: TILOS: A posynomial programming approach to transistor sizing. Proc. ICCAD (1985). Digest of Technical Papers, 326-328.
    • Fishburn, J. and Dunlop, A.: TILOS: A posynomial programming approach to transistor sizing. Proc. ICCAD (1985). Digest of Technical Papers, 326-328.
  • 8
    • 0025721599 scopus 로고
    • Transistor sizing for large combinational digital CMOS circuits
    • Heusler, L.S., and Fichtner, W.: Transistor sizing for large combinational digital CMOS circuits. Integration, the VLSI Journal 10, 1991, 155-168.
    • (1991) Integration, the VLSI Journal , vol.10 , pp. 155-168
    • Heusler, L.S.1    Fichtner, W.2
  • 11
    • 41549134131 scopus 로고    scopus 로고
    • Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation
    • Khandelwal, V., and Srivastava, A.: Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. IEEE Trans. on Computer-Aided Design 27, 2008, 610-620.
    • (2008) IEEE Trans. on Computer-Aided Design , vol.27 , pp. 610-620
    • Khandelwal, V.1    Srivastava, A.2
  • 13
    • 0027701389 scopus 로고
    • An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
    • Sapatnekar, S.S., Rao, V.B., Vaidya, P.M., and Kang, S.-M.: An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization. IEEE Trans. on Computer-Aided Design 12 (11), 1993, 1621-1634.
    • (1993) IEEE Trans. on Computer-Aided Design , vol.12 , Issue.11 , pp. 1621-1634
    • Sapatnekar, S.S.1    Rao, V.B.2    Vaidya, P.M.3    Kang, S.-M.4
  • 15
    • 33750594762 scopus 로고    scopus 로고
    • Statistical Timing Yield Optimization by Gate Sizing
    • Sinha, D., Shenoy, N.V., and Zhou, H.: Statistical Timing Yield Optimization by Gate Sizing. IEEE Transactions on VLSI Systems 14 (10), 2006, 1140-1146.
    • (2006) IEEE Transactions on VLSI Systems , vol.14 , Issue.10 , pp. 1140-1146
    • Sinha, D.1    Shenoy, N.V.2    Zhou, H.3
  • 17
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    • Gate sizing by Lagrangian relaxation revisited. Proc
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    • Wang, J.1    Das, D.2    Zhou, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.