A sequential quadratic programming approach to concurrent gate and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 8, 1997, Pages 867-881

  Menezes, Noel ^a   Baldick, Ross ^b   Pileggi, Lawrence T ^c  

^a INTEL CORPORATION   (United States)

^b The University of Texas at Austin   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INTERCONNECTION NETWORKS; LOGIC GATES;

ELMORE DELAY APPROXIMATION; SEQUENTIAL QUADRATIC PROGRAMMING (SQP);

COMPUTER AIDED LOGIC DESIGN;

EID: 0031197346     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.644611     Document Type: Article

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