Incremental gate sizing for late process changes

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2010, Pages 215-221

  Lee, John ^a   Gupta, Puneet ^a  

^a Engineering IV   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; DESIGN CYCLE; ENGINEERING CHANGE ORDERS; GATE SIZING; LINEAR PROGRAMMING OPTIMIZATION; MANUFACTURING PROCESS; PHYSICAL-DESIGN TOOLS; PROCESS CHANGE;

COST BENEFIT ANALYSIS; DESIGN; GATES (TRANSISTOR); INDUSTRIAL ENGINEERING; MANUFACTURE; OPTIMIZATION; PRODUCTION ENGINEERING;

PROBLEM SOLVING;

EID: 78650755007     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647778     Document Type: Conference Paper

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