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Volumn , Issue , 2011, Pages 167-174

Lagrangian relaxation for gate implementation selection

Author keywords

gate sizing; lagrangian relaxation; low power; optimization; threshold voltage

Indexed keywords

CELL LIBRARY; CIRCUIT OPTIMIZATION; DESCENT METHOD; DISCRETE SPACES; FASTER CONVERGENCE; GATE SIZING; LAGRANGIAN DUAL PROBLEM; LAGRANGIAN MULTIPLIERS; LAGRANGIAN RELAXATION; LAGRANGIAN RELAXATIONS; LOW POWER; MULTI OBJECTIVE; SOLUTION QUALITY;

EID: 79955073967     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1960397.1960436     Document Type: Conference Paper
Times cited : (11)

References (21)
  • 1
    • 0022231945 scopus 로고
    • TILOS: A posynomial programming approach to transistor sizing
    • J. Fishburn and A. Dunlop. "TILOS: A posynomial programming approach to transistor sizing," In Proc. of ICCAD, pp. 326-328, 1985.
    • (1985) Proc. of ICCAD , pp. 326-328
    • Fishburn, J.1    Dunlop, A.2
  • 2
    • 0033100297 scopus 로고    scopus 로고
    • Design and optimization of dual threshold circuits for low voltage low power application
    • Mar.
    • L. Wei, Z. Chen, K. Roy, and V. De. "Design and optimization of dual threshold circuits for low voltage low power application," IEEE Trans. VLSI, vol. 7, no. 1, pp. 16-24, Mar. 1999.
    • (1999) IEEE Trans. VLSI , vol.7 , Issue.1 , pp. 16-24
    • Wei, L.1    Chen, Z.2    Roy, K.3    De, V.4
  • 3
    • 0033359507 scopus 로고    scopus 로고
    • Low power synthesis of dual threshold voltage CMOS circuits
    • V. Sundararajan and K.K. Parhi. "Low power synthesis of dual threshold voltage CMOS circuits," In Proc. of ISLPED, pp. 139-144, 1999.
    • (1999) Proc. of ISLPED , pp. 139-144
    • Sundararajan, V.1    Parhi, K.K.2
  • 4
    • 23744433702 scopus 로고    scopus 로고
    • Simultaneous Vt selection and assignment for leakage optimization
    • V. Khandelwal, A. Davoodi, and A. Srivastava. "Simultaneous Vt selection and assignment for leakage optimization," IEEE Trans. VLSI, vol. 13, no. 6, pp. 762-765, 2005.
    • (2005) IEEE Trans. VLSI , vol.13 , Issue.6 , pp. 762-765
    • Khandelwal, V.1    Davoodi, A.2    Srivastava, A.3
  • 5
    • 0036907253 scopus 로고    scopus 로고
    • Standby power optimization via transistor sizing and dual threshold voltage assignment
    • M. Ketkar and S. S. Sapatnekar. "Standby power optimization via transistor sizing and dual threshold voltage assignment," In Proc. of ICCAD, pp. 375-378, 2002.
    • (2002) Proc. of ICCAD , pp. 375-378
    • Ketkar, M.1    Sapatnekar, S.S.2
  • 6
    • 1542359159 scopus 로고    scopus 로고
    • Minimizion of dynamic and static power through joint assignment of threshold voltages and sizing optimization
    • D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer. "Minimizion of dynamic and static power through joint assignment of threshold voltages and sizing optimization," In Proc. of ISLPED, pp. 158-162, 2003.
    • (2003) Proc. of ISLPED , pp. 158-162
    • Nguyen, D.1    Davare, A.2    Orshansky, M.3    Chinnery, D.4    Thompson, B.5    Keutzer, K.6
  • 7
    • 33751404357 scopus 로고    scopus 로고
    • Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
    • S. Shah, A. Srivastava, D. Sharma, D. Sylvester, D. Balaauw, and V. Zolotov. "Discrete Vt assignment and gate sizing using a self-snapping continuous formulation," In Proc. of ICCAD, pp. 704-710, 2005.
    • (2005) Proc. of ICCAD , pp. 704-710
    • Shah, S.1    Srivastava, A.2    Sharma, D.3    Sylvester, D.4    Balaauw, D.5    Zolotov, V.6
  • 8
  • 9
    • 84861419836 scopus 로고    scopus 로고
    • Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian relaxation
    • H. Chou, Y. Wang, and C. Chen. "Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian relaxation," In Proc. of ASPDAC, pp. 381-386, 2005.
    • (2005) Proc. of ASPDAC , pp. 381-386
    • Chou, H.1    Wang, Y.2    Chen, C.3
  • 10
    • 57549087959 scopus 로고    scopus 로고
    • A parallel and randomized algorithm for large-scale dual-Vt assignment and continuous gate sizing
    • T.-H. Wu, L. Xie, and A. Davoodi. "A parallel and randomized algorithm for large-scale dual-Vt assignment and continuous gate sizing," In Proc. of ISLPED, pp. 45-50, 2008.
    • (2008) Proc. of ISLPED , pp. 45-50
    • Wu, T.-H.1    Xie, L.2    Davoodi, A.3
  • 11
    • 50249166712 scopus 로고    scopus 로고
    • Gate sizing by Lagrangian relaxation revisited
    • J. Wang, D. Das, and H. Zhou. "Gate sizing by Lagrangian relaxation revisited," In Proc. of ICCAD, pp. 111-118, 2007.
    • (2007) Proc. of ICCAD , pp. 111-118
    • Wang, J.1    Das, D.2    Zhou, H.3
  • 12
    • 0032685389 scopus 로고    scopus 로고
    • Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
    • C. Chen, C. C. N. Chu, and D. F. Wong. "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation," IEEE Trans. CAD, vol. 18, no. 7, pp. 1014-1025, 1999.
    • (1999) IEEE Trans. CAD , vol.18 , Issue.7 , pp. 1014-1025
    • Chen, C.1    Chu, C.C.N.2    Wong, D.F.3
  • 13
    • 0034228756 scopus 로고    scopus 로고
    • A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]
    • K. Kasamsetty, M. Ketkar, and S.S. Sapatnekar. "A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]," IEEE Trans. CAD, vol. 13, no. 6, pp. 779-788, 2000.
    • (2000) IEEE Trans. CAD , vol.13 , Issue.6 , pp. 779-788
    • Kasamsetty, K.1    Ketkar, M.2    Sapatnekar, S.S.3
  • 14
    • 33751423598 scopus 로고    scopus 로고
    • ConvexFit: An optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing
    • S. Roy, W. Chen, and C.C. Chen. "ConvexFit: An optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing," In Proc. of ICCAD, pp. 196-204, 2005.
    • (2005) Proc. of ICCAD , pp. 196-204
    • Roy, S.1    Chen, W.2    Chen, C.C.3
  • 15
    • 34547315715 scopus 로고    scopus 로고
    • Gate sizing for cell library based designs
    • S. Hu, M. Ketkar, and J. Hu. "Gate sizing for cell library based designs," In Proc. of DAC, pp. 847-852, 2007.
    • (2007) Proc. of DAC , pp. 847-852
    • Hu, S.1    Ketkar, M.2    Hu, J.3
  • 16
    • 70349085774 scopus 로고    scopus 로고
    • A new algorithm for simultaneous gate sizing and threshold voltage assignment
    • Y. Liu and J. Hu, "A new algorithm for simultaneous gate sizing and threshold voltage assignment," In Proc. of ISPD, pp. 27-34, 2009.
    • (2009) Proc. of ISPD , pp. 27-34
    • Liu, Y.1    Hu, J.2
  • 17
    • 0036911571 scopus 로고    scopus 로고
    • Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
    • H. Tennakoon and C. Sechen. "Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step," In Proc. of ICCAD, pp. 395-402, 2001.
    • (2001) Proc. of ICCAD , pp. 395-402
    • Tennakoon, H.1    Sechen, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.