Gate sizing and device technology selection algorithms for high-performance industrial designs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 724-731

  Ozdal, Muhammet Mustafa ^a   Burns, Steven ^a   Hu, Jiang ^b  

^a INTEL CORPORATION   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE TECHNOLOGIES; DISCRETE CELLS; GATE SIZING; GRAPH MODEL; GRAPH PROBLEMS; HIGH-PERFORMANCE DESIGN; HIGH-PERFORMANCE MICROPROCESSORS; INDUSTRIAL OPTIMIZATION; LAGRANGIAN; LAGRANGIAN RELAXATIONS; LEAKAGE POWER REDUCTION; LIBRARY DATA; LOSS OF ACCURACY; LOW POWER; PRACTICAL PROBLEMS; SIGN-OFF; STATE OF THE ART; TIMING ANALYSIS;

ALGORITHMS; COMPUTER AIDED DESIGN; GATES (TRANSISTOR); LAGRANGE MULTIPLIERS; OPTIMIZATION;

INDUSTRY;

EID: 84862921936     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105409     Document Type: Conference Paper

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