Gate sizing for cell-library-based designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 818-825

  Hu, Shiyan ^a   Ketkar, Mahesh ^b   Hu, Jiang ^c  

^a Michigan Technological University   (United States)

^b INTEL CORPORATION   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

Discretization; Dynamic programming (DP); Gate sizing; Pruning; Sparse cell library

Indexed keywords

AREA COST; CELL LIBRARY; CELL SIZE; DISCRETIZATION; DISCRETIZATIONS; EFFECTIVE ALGORITHMS; GATE SIZING; NOVEL TECHNIQUES; SEMICONDUCTOR PRODUCTS; TIME-TO-MARKET; TIMING CONSTRAINTS;

ALGORITHMS; TIME MEASUREMENT; TIMING CIRCUITS;

DYNAMIC PROGRAMMING;

EID: 77955191978     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. J. Fishburn and A. Dunlop, "Tilos: A polynomial programming approach to transistor sizing," in Proc. Int. Conf. Comput.-Aided Des., 1985, pp. 326-328.
2. C.-P. Chen, C. Chu, and D. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 7, pp. 1014-1025, Jul. 1999.
3. S. Boyd, S. Kim, D. Patil, and M. Horowitz, "Digital circuit optimization via geometric programming," Oper. Res., vol. 53, no. 6, pp. 899-932, Nov./Dec. 2005. (Pubitemid 43061808)
4. N. Hanchate and N. Ranganathan, "Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory," IEEE Trans. Comput., vol. 55, no. 8, pp. 1011-1023, Aug. 2006. (Pubitemid 44193987)
5. F. Beeftink, P. Kudva, D. Kung, and L. Stok, "Gate-size selection for standard cell libraries," in Proc. Int. Conf. Comput.-Aided Des., 1998, pp. 545-550.
6. W. Chuang, S. Sapatnekar, and I. Hajj, "Delay and area optimization for discrete gate sizes under double-sided timing constraints," in Proc. IEEE Custom Integr. Circuits Conf., 1993, pp. 9.4.1-9.4.4.
7. O. Coudert, "Gate sizing for constrained delay/power/area optimization," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 465-472, Dec. 1997.
8. A. Gionis, P. Indyk, and R. Motwani, "Similarity search in high dimensions via hashing," in Proc. ACM Int. Conf. Very Large Data Bases, 1999, pp. 518-529.
9. K. Kasamasetty, M. Ketkar, and S. S. Sapatnekar, "A new class of convex functions for delay modeling and its application to the transistor sizing problem," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 7, pp. 779-788, Jul. 2000.