A length-matching routing algorithm for high-performance printed circuit boards

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 12, 2006, Pages 2784-2793

  Ozdal, Muhammet Mustafa ^b,c   Wong, Martin D F ^a,b  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Algorithms; Lagrangian relaxation; Printed circuit board (PCB); Routing; Very large scale integration (VLSI)

Indexed keywords

CLOCK FREQUENCIES; LAGRANGIAN RELAXATION; ROUTING PROBLEMS;

ALGORITHMS; CONSTRAINT THEORY; PRINTED CIRCUIT BOARDS; PROBLEM SOLVING; VLSI CIRCUITS;

ROUTERS;

EID: 33845635280     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882584     Document Type: Article

References (25)

1. V. Betz and J. Rose, "Directional bias and non-uniformity in FPGA global routing architectures," in Proc. ICCAD, 1996, pp. 652-659.
2. _, "VPR: A new packing, placement and routing tool for FPGA research," in Proc. 7th Int. Workshop Field-Programmable Logic, 1997, pp. 213-222.
3. K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung, and D. Zhou, "On high-speed VLSI interconnects: Analysis and design," in Proc. Asia-Pacific Conf. Circuits Syst., 1992, pp. 35-40.
4. J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao, "Bounded-skew clock and steiner routing," ACM Trans. Design Automat. Electron. Syst., vol. 3, no. 3, pp. 341-388, Jul. 1998.
5. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, "Performance-driven global routing for cell based IC's," in Proc. IEEE Int. Conf. Comput. Des., 1991, pp. 170-173.
6. _, "Probably good performance-driven global routing," IEEE Trans. Comput.-AidedDesign Integr. Circuits Syst., vol. 11, no. 6, pp. 739-752, Jun. 1992.
7. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, MA: MIT Press, 1992.
8. A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Juki, P. Kozak, and M. Wiesel, "Chip layout optimization using critical path weighting," in Proc. Des. Autom. Conf., 1984, pp. 133-136.
9. C. Ebeling, L. McMurchie, and S. A. Hauck, "Placement and routing tools for the triptych FPGA," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 4, pp. 473-482, Dec. 1995.
10. M. L. Fisher, "The Lagrangian relaxation method for solving integer programming problems," Manage. Sci vol. 27, no. 1, pp. 1-18, 1981.
11. _, "An applications oriented guide to Lagrangian relaxation," Interfaces, vol. 15, no. 2, pp. 10-21, 1985.
12. A. M. Geoffrion, "Lagrangian relaxation and its uses in integer programming," Math. Program., vol. 2, pp. 82-114, 1974.
13. X. Guan, P. B. Luh, and L. Zhang, "Nonlinear approximation method in Lagrangian relaxation-based algorithms for hydrothermal scheduling," IEEE Trans. Power Syst., vol. 10, no. 2, pp. 772-778, May 1995.
14. X. H. Guan, Q. Z. Zhai, and F. Lai, "New Lagrangian relaxation based algorithm for resource scheduling with homogeneous subproblems," J. Optim. Theory AppL, vol. 113, no. 1, pp. 65-82, 2002.
15. M. H. Held, P. Wolfe, and H. D. Crowder, "Validation of subgradient optimization," Math. Program., vol. 6, no. 1, pp. 62-88, 1974.
16. D. J.-H. Huang, A. B. Kahng, and C.-W. A. Tsao, "On the bounded-skew clock and steiner routing problems," in Proc. 32nd ACM/IEEE Des. Autoin. Conf., 1995, pp. 508-513.
17. A. B. Kahng and G. Robins, On Optimal Interconnections in VLSI. Norwell, MA: Kluwer, 1995.
18. E. Kuh, M. A. B. Jackson, and M. Marek-Sadowska, "Timing-driven routing for building block layout," in Proc. IEEE Int. Symp. Circuits Syst., 1987, pp. 518-519.
19. S. Lee and M. D. F. Wong, "Timing-driven routing for FPGAs based on Lagrangian relaxation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 4, pp. 506-510, Apr. 2003.
20. M. Pecht and Y. T. Wong, Advanced Routing of Electrical Modules, Boca Raton, FL: CRC Press, 1996.
21. S. Prastjutrakul and W. J. Kubitz, "A timing-driven global router for custom chip design," in Proc. IEEE Int. Conf. Comput.-Aided Des., 1990, pp. 48-51.
22. A. Renaud, "Daily generation management at Electricite de France: Form planning toward real time," IEEE Trans. Autom. Control, vol. 38, no. 7, pp. 1080-1093, Jul. 1993.
23. L. W. Ritchey. (2000, Dec.). "Busses: What are they and how do they work?" Print. Circuit Des. Mag. [Online], Available: http://www. speedingedge.com/PDF-Files/busses.pdf
24. C.-W. A. Tsao and C.-K. Koh, "UST/DME: A clock tree router for general skew constraints," ACM Trans. Des. Automat. Electron. Syst., vol. 7, no. 3, pp. 359-379, Jul. 2002.
25. S. J. Wang, S. M. Shahidehpour, D. S. Kirschen, S. Mokhtari, and G. D. Irisari, "Short-term generation scheduling with transmission constraints using augmented Lagrangian relaxation," IEEE Trans. Power Syst., vol. 10, no. 3, pp. 1294-1301, Aug. 1995.