A new algorithm for simultaneous gate sizing and threshold voltage assignment

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2009, Pages 27-34

  Liu, Yifang ^a   Hu, Jiang ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Gate sizing; Threshold voltage assignment

Indexed keywords

BENCHMARK CIRCUIT; BI-DIRECTIONAL SEARCH; CIRCUIT TIMING; COMBINATORIAL APPROACH; CONTINUOUS OPTIMIZATION; EXISTING METHOD; GATE SIZING; LOCAL OPTIMA; POWER DISSIPATION; POWER OPTIMIZATION; TIMING CONSTRAINTS;

GATES (TRANSISTOR); HEURISTIC METHODS; THRESHOLD VOLTAGE; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 70349085774     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1514932.1514940     Document Type: Conference Paper

References (22)

1. J. Fishburn and A. Dunlop. TILOS: A Posynomial Programming Approach to Transistor Sizing. In Proc. of ICCAD, pp 326-328, 1985.
2. C. Chen, C. C. N. Chu, and D. F. Wong. Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian relaxation. In IEEE Trans. CAD, 18(7):1014-1025, 1999.
3. O. Coudert. Gate sizing for constrained delay/power/area optimization. ID IEEE Trans. VLSI, 5(4):479-484, 1997.
4. P. K. Chan. Algorithms for Library-Specific Sizing of Combinational Logic. In Proc. of DAC, pp 353-356, 1990.
5. S. Hu, M. Ketkar, and J. Hu. Gate Sizing for Cell Library Based Designs. In Proc. of DAC, pp 847-852, 2007.
6. L. Wei, Z. Chen, K. Roy, and V. De. Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Application. In IEEE Trans. VLSI, 7(1):16-24, 1999.
7. V. Sundararajan and K.K. Parhi. Low Power Synthesis of Dual Threshold Voltage CMOS Circuits. In Proc. of ISLPED, pp 139-144, 1999.
8. V. Khandelwal, A. Davoodi, and A. Srivastava. Simultaneous Vt selection and assignment for leakage optimization. In IEEE Trans. VLSI, 13(6):762-765, 2005.
9. M. Ketkar and S. S. Sapatnekar. Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment. In Proc. of ICCAD, pp 375-378, 2002.
10. D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer. Minimizion of Dynamic and Static Power Through Joint Assignement of Threshold Voltages and Sizing Optimization. In Proc. of ISLPED, pp 158-162, 2003.
11. S. Shah, A. Srivastava, D. Sharma, D. Sylvester, D. Balaauw, and V. Zolotov. Discrete Vt Assignment and Gate Sizing Using a Self-Snapping Continuous Formulation. In Proc. of ICCAD, pp 704-710, 2005.
12. S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda, and D. Blaauw. Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing. In Proc. of DAC, pp 436-441, 1999.
13. H. Chou, Y. Wang, and C. Chen. Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian relaxation. In Proc. of ASPDAC, pp 381-386, 2005.
14. T.-H. Wu, L. Xie, and A. Davoodi. A parallel and randomized algorithm for large-scale dual-Vt assignment and continuous gate sizing. In Proc. of ISLPED, pp 45-50, 2008.
15. K. Kasamsetty, M. Ketkar, and S.S. Sapatnekar. A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]. In IEEE Trans. CAD, 13(6):779-788, 2000.
16. S. Roy, W Chen, and C.C. Chen. ConvexFit: An Optimal Minimum-Error Convex Fitting and Smoothing Algorithm with Application to Gate-Sizing. In Proc. of ICCAD, pp 196-204, 2005.
17. J. Lillis, C.K. Cheng, and T.Y. Lin. Optimal Wire sizing and Buffer Insertion for Low Power and a Generalized Delay Model. In IEEE Journal of Solid-State Circuits, 31(3):437-447, 1996.
18. C.L. Ratzlaff, N. Gopal, and L.T. Pillage. RICE: Rapid interconnect circuit evaluator. In Proc. of DAC, pp 555-560, 1999.
19. J. Qian, S. Pullela, and L.T. Pillage. Modeling the Effective Capacitance of RC Interconnect. In IEEE Trans. CAD, 13(12):1526-1535, 1994.
20. M. Bazaraa, H. Sherali, and C. Shetty. Nonlinear Programming: Theory and Algorithms. In Wiley, New York, NY, 2nd edition, 2003.
21. E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, PR. Stephan, R.K. Brayton, and A.L. Snagiovanni. SIS: a system for sequential circuit synthesis. In Memorandum no. M92/41, ERL, UCB, 1992.
22. CPMO-constrained placement by multilevel optimization. http://ballade.cs.ucla.edu/cpmo. Computer Science Department, UCLA.