Estimating information-theoretical nand flash memory storage capacity and its implication to memory system design space exploration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 9, 2012, Pages 1705-1714

  Dong, Guiqiang ^a   Pan, Yangyang ^a   Xie, Ningde ^b   Varanasi, Chandra ^c   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b INTEL CORPORATION   (United States)

^c MICRON TECHNOLOGY INC   (United States)

Author keywords

Endurance; information theory; interference; model; nand flash; retention; storage capacity; tradeoff

Indexed keywords

BCH CODE; CYCLING EFFECTS; CYCLING ENDURANCE; DESIGN SPACE EXPLORATION; DESIGN TECHNIQUE; ERROR CORRECTION CODES; MEMORY SYSTEMS; NAND FLASH; NAND FLASH MEMORY; PRACTICAL IMPORTANCE; PROGRAM/ERASE; RETENTION; STORAGE CAPACITY; STORAGE EFFICIENCY; STORAGE RELIABILITY; SYSTEM DESIGNERS; SYSTEM LEVELS; THEORETICAL LIMITS; TRADEOFF; USER DATA;

CELLS; COMMERCE; DURABILITY; FAULT TOLERANCE; FLASH MEMORY; INFORMATION THEORY; MODELS; NAND CIRCUITS; REDUNDANCY; SYSTEMS ANALYSIS; WAVE INTERFERENCE;

CYTOLOGY;

EID: 84863985865     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2160747     Document Type: Article

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