Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies

CF '12 - Proceedings of the ACM Computing Frontiers Conference

Volumn , Issue , 2012, Pages 95-102

  Yoon, Doe Hyun ^a   Gonzalez, Tobin ^a   Ranganathan, Parthasarathy ^a   Schreiber, Robert S ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

latency power tradeoff; memory hierarchy; nonvolatile memory

Indexed keywords

CACHE HIERARCHIES; LATENCY-POWER TRADEOFF; MAIN MEMORY; MEMORY ACCESS TIME; MEMORY HIERARCHY; MEMORY MODELS; NON-VOLATILE MEMORIES; PERFORMANCE MODEL; SCIENTIFIC APPLICATIONS;

BENCHMARKING; COMMERCE; DYNAMIC RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 84862668634     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2212908.2212923     Document Type: Conference Paper

References (29)

1. Graph 500. http://www.graph500.org/.
2. X. Dong, X. Wu, Y. Xie, Y. Chen, and H. Li. Stacking MRAM atop microprocessors: An architecture-level evaluation. IET Computers & Digital Techniques, 5(3), 2011.
3. B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45:1180-1194, Oct. 1996.
4. A. Jaleel, K. Theobald, S. C. Steely Jr., and J. Emer. High performance cache replacement using re-reference interval prediction (RRIP). In Proc. the 37th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2010.
5. Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie. Energy- and endurance-aware design of phase change memory caches. In Proc. the Conf. Design Automation and Test in Europe (DATE), Mar. 2010.
6. N. P. Jouppi and S. J. E. Wilton. Tradeos in two-level on-chip caching. In Proc. the 21st Ann. Int'l Symp. Computer Architecture (ISCA), Apr. 1994.
7. I. S. Kim, S. L. Cho, D. H. Im, E. H. Cho, D. H. Kim, G. H. Oh, D. H. Ahn, S. O. Park, S. W. Nam, J. T. Moon, and C. H. Chung. High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications. In Proc. the Symp. VLSI Technology (VLSIT), Jun.
8. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable DRAM alternative. In Proc. the 36th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2009.
9. S. Li, K. Chen, J. H. Ahn, J. B. Brockman, and N. P. Jouppi. CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. In Proc. the IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), Nov. 2011.
10. J. M. Lin, Y. Chen, W. Li, Z. Tang, and A. Jaleel. Memory characterization of SPEC CPU 2006 benchmark suite. In Proc. the 11th Workshop for Computer Architecture Evaluation of Commercial Workloads (CAECW), Feb. 2008.
11. G. H. Loh and M. D. Hill. Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. In Proc. the 44th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Dec. 2011.
12. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. PIN: Building customized program analysis tools with dynamic instrumentation. In Proc. the ACM Conf. Programming Language Design and Implementation (PLDI), Jun. 2005.
13. N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. CACTI 6.0. Technical report, HP Labs., Apr. 2009.
14. R. C. Murphy, A. Rodrigues, P. Kogge, and K. Underwood. The implications of working set analysis on supercomputing memory hierarchy design. In Proc. the International Conference on Supercomputing (ICS), Jun. 2006.
15. S. Przybylski, M. Horowitz, and J. Hennessy. Characteristics of performance-optimal multi-level cache hierarchies. In Proc. the 16th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 1989.
16. M. K. Qureshi. Pay-As-You-Go: Low overhead hard-error correction for phase change memories. In Proc. the 44th IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Dec. 2011.
17. M. K. Qureshi, M. Fraceschini, L. Lastras, and J. Karidis. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In Proc. the 37th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2010.
18. M. K. Qureshi, M. Franceschini, and L. Lastras. Improving read performance of phase change memories via write cancellation and write pausing. In Proc. the 16th Int'l Symp. High-Performance Computer Architecture (HPCA), Jan. 2010.
19. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely Jr., and J. Emer. Adaptive insertion policies for high-performance caching. In Proc. the 34th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2007.
20. M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abail. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In Proc. the 42nd IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Dec. 2009.
21. M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high-performance main memory system using phase-change memory technology. In Proc. the 36th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2009.
22. Sandia National Laboratories. Mantevo project. https://software.sandia. gov/mantevo/index.html.
23. S. Schechter, G. H. Loh, K. Strauss, and D. Burger. Use ECP, not ECC, for hard failures in resistive memories. In Proc. the 37th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2010.
24. N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H.-H. S. Lee. SAFER: Stuck-at-fault error recovery for memories. In Proc. the 43rd IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Dec. 2010.
25. Standard Performance Evaluation Corporation. SPEC CPU 2006. http://www.spec.org/cpu2006/, 2006.
26. G. Sun, C. J. Hughes, C. Kim, J. Zhao, C. Xu, Y. Xie, and Y.-K. Chen. Moguls: A model to explore the memory hierarchy for bandwidth improvements. In Proc. the 38th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2011.
27. D. H. Woo, N. H. Seong, D. L. Lewis, and H.-H. S. Lee. An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. In Proc. the 16th Int'l Symp. High-Performance Computer Architecture (HPCA), Jan. 2010.
28. C. Xu, X. Dong, N. P. Jouppi, and Y. Xie. Design implications of memristor-based RRAM cross-point structures. In Proc. the Design, Automation and Test in Europe (DATE), Mar. 2011.
29. D. H. Yoon, N. Muralimanohar, J. Chang, P. Ranganathan, N. P. Jouppi, and M. Erez. FREE-p: Protecting non-volatile memory against both hard and soft errors. In Proc. the 17th Int'l Symp. High-Performance Computer Architecture (HPCA), Feb. 2011.