Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation

IET Computers and Digital Techniques

Volumn 5, Issue 3, 2011, Pages 213-220

  Dong, X ^a   Wu, X ^b   Xie, Y ^a   Chen, Y ^c   Li, H ^d  

^a The Pennsylvania State University   (United States)

^b QUALCOMM INC   (United States)

^c University of Pittsburgh   (United States)

^d POLYTECHNIC UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; CMOS LOGIC; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; DYNAMIC RANDOM ACCESS MEMORY; FABRICATION PROCESS; HIGH DENSITY; INSTRUCTION PER CYCLES; MAGNETIC RANDOM ACCESS MEMORIES; MANUFACTURING COST; MEMORY TECHNOLOGY; MICROPROCESSOR CORE; NONVOLATILITY; SIMULATION RESULT; STAND-BY LEAKAGE; STATIC RANDOM ACCESS MEMORY;

MAGNETIC LEAKAGE; MAGNETIC STORAGE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; MRAM DEVICES; STATIC RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 79959768185     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2009.0091     Document Type: Article

References (23)

1. Dong, X., Wu, X., and Sun, G.: et al. 'Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement', Proc. Design Automation Conf., 2008, p. 554-559
2. Motoyoshi, M., Yamamura, I., and Ohtsuka, W.: et al. 'A study for 0.18 μm high-density MRAM', Proc. Int. Symp. on VLSI Technology, 2004, p. 22-23
3. Tanizaki, H., Tsuji, T., and Otani, J.: et al. 'A high-density and high-speed 1T-4MTJ MRAM with voltage offset self-reference sensing scheme', Proc. Asian Solid-State Circuits Conf., 2006, p. 303-306
4. Tsuchida, K., Inaba, T., and Fujita, K.: et al. 'A 64 Mb MRAM with clamped-reference and adequate-reference schemes', Proc. Int. Solid-State Circuits Conf., 2010, p. 268-269
5. Hosomi, M., Yamagishi, H., and Yamamoto, T.: et al. 'A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM', Proc. Int. Electron Devices Meeting, 2005, p. 459-462
6. Kawahara, T., Takemura, R., and Miura, K.: et al. '2 Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read', Proc. Int. Solid-State Circuits Conf., 2007, p. 480-617
7. 'On-chip MRAM as a high-bandwidth low-latency replacement for DRAM physical memories', Tech., UT Austin, 2002
8. 'Assessment of MRAM technology characteristics and architectures', Tech., UT-Austin, 2002
9. Reohr, W., Honigschmid, H., and Robertazzi, R.: et al. 'Memories of tomorrow', IEEE Circuits Devices Mag., 2002, 18, (5), p. 17-2710.1109/MCD.2002.1035347 8755-3996
10. Xie, Y., Loh, G.H., Black, B., and Bernstein, K.: 'Design space exploration for 3D architectures', ACM J. Emerg. Technol. Comput. Syst., 2006, 2, (2), p. 65-10310.1145/1148015.1148016
11. Chen, Y., Wang, X., Li, H., Liu, H., and Dimitrov, D.V.: 'Design margin exploration of spin-torque transfer RAM (SPRAM)', Proc. Int. Symp. on Quality Electronic Design, 2008, p. 684-690
12. Zhao, W., Belhaire, E., and Mistral, Q.: et al. 'Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic- CMOS design', Proc. Int. Behavioral Modeling and Simulation Workshop, 2006, p. 40-43
13. 'CACTI 5.1 Technical Report', Tech., HP Labs, 2008
14. The MOSIS Service, available at: http://www.mosis.com/technical/designrules/scmos/, 2008
15. 'Alpha ev7 processor: a high-performance tradition continues', Microprocessor Report, 2005
16. Magnusson, P.S., Christensson, M., and Eskilson, J.: et al. 'Simics: a full system simulation slatform', Computer, 2002, 35, (2), p. 50-5810.1109/2.982916 0018-9162
17. NASA Advanced Supercomputing Division: NAS Parallel Benchmarks: available at: http://www.nas.nasa.gov/Resources/Software/npb.html
18. Bienia, C., Kumar, S., Singh, J.P., and Li, K.: 'The PARSEC benchmark suite: characterization and architectural implications', Proc. Int. Conf. on Parallel Architectures and Compilation Techniques, 2008, p. 72-81
19. Liu, C., Ganusov, I., Burtscher, M., and Tiwari, S.: 'Bridging the processor-memory performance gap with 3D IC technology', IEEE Des. Test Comput., 2005, 22, (6), p. 556-56410.1109/MDT.2005.134 0740-7475
20. Loi, G.L., Agrawal, B., and Srivastava, N.: et al. 'A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy', Proc. Design Automation Conf., 2006, p. 991-996
21. Schechter, S., Loh, G.H., Straus, K., and Burger, D.: 'Use ECP, not ECC, for hard failures in resistive memories', Proc. Int. Symp. on Computer Architecture, 2010, p. 141-152
22. Zhou, P., Zhao, B., Yang, J., and Zhang, Y.: 'A durable and energy efficient main memory using phase change memory technology', Proc. Int. Symp. on Computer Architecture, 2009, p. 14-23
23. Qureshi, M.K., Srinivasan, V., and Rivers, J.A.: 'Scalable high performance main memory system using phase-change memory technology', Proc. Int. Symp. on Computer Architecture, 2009, p. 24-33