Pay-As-You-Go: Low-overhead hard-error correction for phase change memories

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 318-328

  Qureshi, Moinuddin K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

error correction; hard faults; phase change memory

Indexed keywords

COST-SENSITIVE; HARD FAULTS; HIGH VARIABILITY; LONG LIFETIME; LOW-LATENCY; MEMORY CAPACITY; PAY-AS-YOU-GO; PHASE CHANGE; STORAGE OVERHEAD;

ERROR CORRECTION; WIRELESS SENSOR NETWORKS;

PHASE CHANGE MEMORY;

EID: 84858775429     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155658     Document Type: Conference Paper

References (10)

1. Int'l Technology Roadmap for Semiconductors (ITRS). http://www.itrs.net/ Links/2008ITRS/Home2008.htm.
2. E. Ipek et al. Dynamically replicated memory: building reliable systems from nanoscale resistive memories. ASPLOS-15, 2010.
3. M. Qureshi et al. Scalable high performance main memory system using phase-change memory technology. In ISCA-36, 2009.
4. M. K. Qureshi et al. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In MICRO-42, 2009.
5. S. Schechter et al. Use ECP, not ECC, for hard failures in resistive memories. In ISCA-2010.
6. N. H. Seong et al. SAFER: Stuck At Fault Error Recovery for Memories. In MICRO-2010.
7. N. H. Seong et al. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In ISCA-37, 2010.
8. J. J. Shedletsky. Error correction by alternate-data retry. IEEE Trans. Comput., 27, February 1978.
9. D. H. Yoon and M. Erez. Virtualized and flexible ecc for main memory. In ASPLOS-15, 2010.
10. D. H. Yoon et al. FREE-p: Protecting non-volatile memory against both hard and soft errors. In HPCA-2011.