An analytical model for designing memory hierarchies

IEEE Transactions on Computers

Volumn 45, Issue 10, 1996, Pages 1180-1194

  Jacob, Bruce L ^a,c   Chen, Peter M ^a,c   Silverman, Seth R ^b   Mudge, Trevor N ^a,c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c IEEE

Author keywords

and storage hierarchies; Cache; Memory; Optimization of cache configurations; Trace driven simulations

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; MATHEMATICAL MODELS; NUMERICAL ANALYSIS; OPTIMIZATION; PERFORMANCE; SYSTEMS ANALYSIS;

CACHE CONFIGURATION; MEMORY HIERARCHY; TRACE DRIVEN SIMULATION; WORKLOAD LOCALITY;

BUFFER STORAGE;

EID: 0030262662     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.543711     Document Type: Article

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