Tradeoffs in two-level on-chip caching

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 1994, Pages 34-45

  Jouppi, Norman P ^a   Wilton, Steven J E ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CHANNEL CAPACITY; COMPUTER ARCHITECTURE; CRITICAL PATH ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER); VIRTUAL STORAGE;

LATENCY; MIXED SECOND LEVEL CACHE; TWO LEVEL ON CHIP CACHING;

DATA STORAGE EQUIPMENT;

EID: 0028201665     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)