-
1
-
-
0035394088
-
Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits
-
DOI 10.1109/81.933328, PII S1057712201053922
-
I.M. Filanovsky and A. Allam, "Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits," IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 48, no. 7, pp. 876-884, Jul. 2001. (Pubitemid 32694330)
-
(2001)
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
, vol.48
, Issue.7
, pp. 876-884
-
-
Filanovsky, I.M.1
Allam, A.2
-
2
-
-
34748845056
-
On the scaling of temperature-dependent effects
-
DOI 10.1109/TCAD.2007.895774
-
J. C. Ku and Y. Ismail, "On the scaling of temperature-dependent effects," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 10, pp. 1882-1888, Oct. 2007. (Pubitemid 47483029)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.10
, pp. 1882-1888
-
-
Ku, J.C.1
Ismail, Y.2
-
3
-
-
0041633858
-
Parameter variations and impact on circuits and microarchitecture
-
IEEE 40th Design Autom. Conf. (DAC'03), Jun
-
S. Borkar et al., "Parameter variations and impact on circuits and microarchitecture," in Proc. ACM IEEE 40th Design Autom. Conf. (DAC'03), Jun. 2003, pp. 338-342.
-
(2003)
Proc. ACM
, pp. 338-342
-
-
Borkar, S.1
-
5
-
-
77955121837
-
Temperature-aware delay borrowing for energy-efficient low-voltage link design
-
May
-
D. Wolpert, B. Fu, and P. Ampadu, "Temperature-aware delay borrowing for energy-efficient low-voltage link design," in Proc. 4th ACM/IEEE Int. Symp. Networks-on-Chip (NoCS'10), May 2010, pp. 107-114.
-
(2010)
Proc. 4th ACM/IEEE Int. Symp. Networks-on-Chip (NoCS'10)
, pp. 107-114
-
-
Wolpert, D.1
Fu, B.2
Ampadu, P.3
-
6
-
-
0029544787
-
Reversal of temperature dependence of integrated circuits operating at very low voltages
-
Dec
-
C. Park et al., "Reversal of temperature dependence of integrated circuits operating at very low voltages," in Proc. Int. Electron Devices Meeting (IEDM'95), Dec. 1995, pp. 71-74.
-
(1995)
Proc. Int. Electron Devices Meeting (IEDM'95)
, pp. 71-74
-
-
Park, C.1
-
7
-
-
0032025630
-
Supply voltage scaling for temperature insensitive CMOS circuit operation
-
PII S1057713098007873
-
A. Bellaouar, A. Fridi, M. Elmasry, and K. Itoh, "Supply voltage scaling for temperature insensitive CMOS circuit operation," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp. 415-417, Mar. 1998. (Pubitemid 128745218)
-
(1998)
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol.45
, Issue.3
, pp. 415-417
-
-
Bellaouar, A.1
Fridi, A.2
Elmasry, M.I.3
Itoh, K.4
-
8
-
-
77955119433
-
Normal and reverse temperature dependence in variation-tolerant nanoscale systems with high-k dielectrics and metal gates
-
Sep
-
D. Wolpert and P. Ampadu, "Normal and reverse temperature dependence in variation-tolerant nanoscale systems with high-k dielectrics and metal gates," Proc. Springer Lecture Notes of the Inst. for Comp. Sci., Social-Informatics and Telecomm. Eng.-3rd Int. ICST Conf. NanoNet 2008, Revised Selected Papers, vol. 3, pp. 14-18, Sep. 2009.
-
(2009)
Proc. Springer Lecture Notes of the Inst. for Comp. Sci., Social-Informatics and Telecomm. Eng.-3rd Int. ICST Conf. NanoNet 2008, Revised Selected Papers
, vol.3
, pp. 14-18
-
-
Wolpert, D.1
Ampadu, P.2
-
9
-
-
34249275660
-
Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits
-
DOI 10.1016/j.mejo.2007.03.011, PII S0026269207000481
-
R. Kumar and V. Kursun, "Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits," Microelectron. J., vol. 38, no. 4-5, pp. 583-594, Apr./May 2007. (Pubitemid 46818335)
-
(2007)
Microelectronics Journal
, vol.38
, Issue.4-5
, pp. 583-594
-
-
Kumar, R.1
Kursun, V.2
-
10
-
-
35048839402
-
Temperature dependence in low power CMOS UDSM process
-
B. Lasbouygues, R. Wilson, P. Maurine, N. Azemard, and D. Auvergne, "Temperature dependence in low power CMOS UDSM process," Springer Lecture Notes in Computer Science, vol. 3254/2004, pp. 110-118.
-
Springer Lecture Notes in Computer Science
, vol.3254
, Issue.2004
, pp. 110-118
-
-
Lasbouygues, B.1
Wilson, R.2
Maurine, P.3
Azemard, N.4
Auvergne, D.5
-
11
-
-
5244323789
-
Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation
-
PII S0268124297819414
-
Y. Cheng et al., "Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation," Semicond. Sci. Technol., vol. 12, no. 11, pp. 1349-1354, Nov. 1997. (Pubitemid 127593624)
-
(1997)
Semiconductor Science and Technology
, vol.12
, Issue.11
, pp. 1349-1354
-
-
Cheng, Y.1
Imai, K.2
Jeng, M.-C.3
Liu, Z.4
Chen, K.5
Hu, C.6
-
12
-
-
77649180896
-
Dual supply voltages and dual clock frequencies for lower clock power and suppressed temperature-gradientinduced clock skew
-
Mar
-
S. A. Tawfik and V. Kursun, "Dual supply voltages and dual clock frequencies for lower clock power and suppressed temperature-gradientinduced clock skew," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 3, pp. 347-355, Mar. 2010.
-
(2010)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.18
, Issue.3
, pp. 347-355
-
-
Tawfik, S.A.1
Kursun, V.2
-
13
-
-
56749083229
-
Temperatureinsensitive synthesis usingmulti-vt libraries
-
May
-
A. Calimera, E. Macii, M. Poncino, and R. I. Bahar, " Temperatureinsensitive synthesis usingmulti-vt libraries," in Proc. 18th ACMGreat Lakes Symp. VLSI (GLSVLSI'08), May 2008, pp. 5-10.
-
(2008)
Proc. 18th ACMGreat Lakes Symp. VLSI (GLSVLSI'08)
, pp. 5-10
-
-
Calimera, A.1
MacIi, E.2
Poncino, M.3
Bahar, R.I.4
-
14
-
-
67649090894
-
An LSI system with locked in temperature insensitive state achieved by using body bias technique
-
May
-
G. Ono, M.Miyazaki, K.Watanabe, and T. Kawahara, "An LSI system with locked in temperature insensitive state achieved by using body bias technique," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'05), May 2005, pp. 632-635.
-
(2005)
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'05)
, pp. 632-635
-
-
Ono, G.1
Miyazaki, M.2
Watanabe, K.3
Kawahara, T.4
-
15
-
-
34548812547
-
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging
-
Feb
-
J. Tschanz et al., "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC'07), Feb. 2007, pp. 292-293.
-
(2007)
Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC'07)
, pp. 292-293
-
-
Tschanz, J.1
-
17
-
-
77953086202
-
Inversed temperature dependence aware clock skew scheduling for sequential circuits
-
Mar
-
J. Long and S. O. Memik, "Inversed temperature dependence aware clock skew scheduling for sequential circuits," in Proc. Design, Autom., Test Eur. (DATE'10), Mar. 2010, pp. 1657-1660.
-
(2010)
Proc. Design, Autom., Test Eur. (DATE'10)
, pp. 1657-1660
-
-
Long, J.1
Memik, S.O.2
-
19
-
-
33750811880
-
Measurements of permittivity, dielectric loss tangent, and resistivity of float-zone silicon at microwave frequencies
-
Nov
-
J. Krupka, J. Breeze,A. Centeno, N. Alford, T. Claussen, and L. Jensen, "Measurements of permittivity, dielectric loss tangent, and resistivity of float-zone silicon at microwave frequencies," IEEE Trans. Microw. Theory Techn., vol. 54, no. 11, pp. 3995-4001, Nov. 2006.
-
(2006)
IEEE Trans. Microw. Theory Techn
, vol.54
, Issue.11
, pp. 3995-4001
-
-
Krupka, J.1
Breezea. Centeno, J.2
Alford, N.3
Claussen, T.4
Jensen, L.5
-
20
-
-
33750596850
-
Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits
-
DOI 10.1109/TCSII.2006.882218
-
R. Kumar and V. Kursun, "Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1078-1082, Oct. 2006. (Pubitemid 44680625)
-
(2006)
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol.53
, Issue.10
, pp. 1078-1082
-
-
Kumar, R.1
Kursun, V.2
-
21
-
-
61349148188
-
Design of thermally robust clock trees using dynamically adaptive clock buffers
-
Feb
-
T. Ragheb et al., "Design of thermally robust clock trees using dynamically adaptive clock buffers," IEEETrans.Circuits Syst. I, Reg. Papers, vol. 56, no. 2, pp. 374-383, Feb. 2009.
-
(2009)
IEEETrans.Circuits Syst. I, Reg. Papers
, vol.56
, Issue.2
, pp. 374-383
-
-
Ragheb, T.1
-
22
-
-
33751399739
-
TACO: Temperature aware clock-tree optimization
-
Nov
-
M. Cho, S. Ahmedtt, and D. Z. Pan, "TACO: Temperature aware clock-tree optimization," in Proc. Int. Conf. Comput. Aided Design (ICCAD'05), Nov. 2005, pp. 582-587.
-
(2005)
Proc. Int. Conf. Comput. Aided Design (ICCAD'05)
, pp. 582-587
-
-
Cho, M.1
Ahmedtt, S.2
Pan, D.Z.3
-
23
-
-
34748864923
-
Minimal skew clock embedding considering time variant temperature gradient
-
DOI 10.1145/1231996.1232036, 1232036, Proceedings of ISPD'07: 2007 International Symposium on Physical Design
-
H. Yu, Y. Hu, C. Liu, and L. He, "Minimal skew clock embedding considering time variant temperature gradient," in Proc. Int. Symp. Phys. Design (ISPD'07), Mar. 2007, pp. 173-180. (Pubitemid 47485400)
-
(2007)
Proceedings of the International Symposium on Physical Design
, pp. 173-180
-
-
Yu, H.1
Hu, Y.2
Liu, C.3
He, L.4
-
24
-
-
34548485765
-
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
-
DOI 10.1016/j.vlsi.2007.03.002, PII S0167926007000156, Power and Timing Modeling, Optimization and Simulation
-
A. Chakraborty et al., "Implementation of a thermal management unit for canceling temperature-dependent clock skew variations," Integr. VLSI J., vol. 41, no. 1, pp. 2-8, Jan. 2008. (Pubitemid 47379887)
-
(2008)
Integration, the VLSI Journal
, vol.41
, Issue.1
, pp. 2-8
-
-
Chakraborty, A.1
Duraisami, K.2
Sathanur, A.3
Sithambaram, P.4
Macii, A.5
Macii, E.6
Poncino, M.7
-
25
-
-
75549091352
-
A 0.52 high-order temperature-compensated voltage reference
-
Jan
-
Y. Liu, Z. Li, P. Luo, and B. Zhang, "A 0.52 high-order temperature-compensated voltage reference," Analog Integr. Circuits Signal Process., vol. 62, no. 1, pp. 17-21, Jan. 2010.
-
(2010)
Analog Integr. Circuits Signal Process
, vol.62
, Issue.1
, pp. 17-21
-
-
Liu, Y.1
Li, Z.2
Luo, P.3
Zhang, B.4
-
26
-
-
39749099415
-
Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip
-
Oct
-
Z. Abuhamdeh et al., "Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip," in Proc. IEEE Int. Test Conf. (ITC'07), Oct. 2007, pp. 1-10.
-
(2007)
Proc. IEEE Int. Test Conf. (ITC'07)
, pp. 1-10
-
-
Abuhamdeh, Z.1
-
27
-
-
77955110181
-
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement
-
Jan
-
Y.-W. Yang and K. S.-M. Li, "Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement," in Proc. Asia South Pacific Design Autom. Conf. (ASP-DAC'09), Jan. 2009, pp. 49-54.
-
(2009)
Proc. Asia South Pacific Design Autom. Conf. (ASP-DAC'09)
, pp. 49-54
-
-
Yang, Y.-W.1
Li, K.S.-M.2
-
28
-
-
70350633959
-
A time-domain sub-micro Watt temperature sensor with digital set-point programming
-
Dec
-
P. Chen, T.-K. Chen, Y.-S. Wang, and C.-C. Chen, "A time-domain sub-micro Watt temperature sensor with digital set-point programming," IEEE Sens. J., vol. 9, no. 12, pp. 1639-1646, Dec. 2009.
-
(2009)
IEEE Sens. J
, vol.9
, Issue.12
, pp. 1639-1646
-
-
Chen, P.1
Chen, T.-K.2
Wang, Y.-S.3
Chen, C.-C.4
-
29
-
-
33947608035
-
Temperature- And voltage-aware timing analysis
-
DOI 10.1109/TCAD.2006.884860
-
B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine, "Temperature- and voltage-aware timing analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 4, pp. 801-815, Apr. 2007. (Pubitemid 46479752)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.4
, pp. 801-815
-
-
Lasbouygues, B.1
Wilson, R.2
Azemard, N.3
Maurine, P.4
-
30
-
-
24644487388
-
Design and validation of a power supply noise reduction technique
-
DOI 10.1109/TADVP.2005.847802
-
G. Ji, T.Arabi, and G. Taylor, "Design and validation of a power supply noise reduction technique," IEEE Trans. Adv. Packaging, vol. 28, no. 3, pp. 445-448, Aug. 2005. (Pubitemid 41263749)
-
(2005)
IEEE Transactions on Advanced Packaging
, vol.28
, Issue.3
, pp. 445-448
-
-
Ji, G.1
Arabi, T.R.2
Taylor, G.3
-
31
-
-
79955582728
-
A sensor system to detect positive and negative temperature dependences
-
Apr
-
D. Wolpert and P. Ampadu, "A sensor system to detect positive and negative temperature dependences," IEEE Trans. Circuits Syst: II: Exp. Briefs, vol. 58, no. 4, pp. 235-239, Apr. 2011.
-
(2011)
IEEE Trans. Circuits Syst: II: Exp. Briefs
, vol.58
, Issue.4
, pp. 235-239
-
-
Wolpert, D.1
Ampadu, P.2
-
32
-
-
33947207004
-
Thermal modeling, analysis, and management in VLSI circuits: Principles and methods
-
DOI 10.1109/JPROC.2006.879797
-
M. Pedram and S. Nazarian, "Thermal modeling, analysis, and management in VLSI circuits: Principles and methods," Proc. IEEE, vol. 94, no. 8, pp. 1487-1501, Aug. 2006. (Pubitemid 46432331)
-
(2006)
Proceedings of the IEEE
, vol.94
, Issue.8
, pp. 1487-1501
-
-
Pedram, M.1
Nazarian, S.2
|