Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits

Microelectronics Journal

Volumn 38, Issue 4-5, 2007, Pages 583-594

  Kumar, Ranjith ^a   Kursun, Volkan ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Minimum energy; Minimum energy delay product; Propagation delay fluctuations; Supply voltage optimization; Temperature variations; Threshold voltage optimization

Indexed keywords

ENERGY EFFICIENCY; OPTIMIZATION; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

MINIMUM ENERGY; MINIMUM ENERGY-DELAY PRODUCT; PROPAGATION DELAY FLUCTUATIONS; SUPPLY VOLTAGE OPTIMIZATION; TEMPERATURE VARIATIONS; THRESHOLD VOLTAGE OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 34249275660     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2007.03.011     Document Type: Article

References (22)

1. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, Parameter variation and impact on circuits and microarchitecture, in: Proceedings of the IEEE/ACM International Design Automation Conference, June 2003, pp. 338-342.
2. Johnson R.W., et al. The changing automotive environment: high temperature electronics. IEEE Trans. Electron. Packag. Manuf. 27 3 (2004) 164-176
3. M.M. Mojarradi, et al., Design challenges for developing new integrated circuits for the robotic exploration of the solar system, Symposium on VLSI Circuits: Digest of Technical Papers, June 2005, pp. 154-155.
4. Kumar R., and Kursun V. Reversed temperature dependent propagation delay characteristics in nanometer CMOS circuits. IEEE Trans. Circuits Syst.-II 53 11 (2006)
5. Cheng Y., Imai K., Jeng M.C., Liu Z., Chen K., and Hu C. Modeling temperature effects of quarter micrometre MOSFET in BSIM3v3 for circuit simulation. Semicond. Sci. Technol. 12 (1997) 1349-1354
6. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, C. Hu, New paradigm of predictive MOSFET and interconnect modeling for early circuit design, in: Proceedings of the IEEE Custom Integrated Circuits Conference, June 2000, pp. 201-204.
7. Liu W., et al. BSIM3v3.2.2 MOSFET Model-User Manual, Department of Electrical and Computer Engineering (1999), University of California, Berkeley
8. Xi X., et al. BSIM4.3.0 MOSFET Model-User Manual, Department of Electrical and Computer Engineering (2003), University of California, Berkeley
9. Taiwan Semiconductor Manufacturing Company (TSMC), 〈http://www.tsmc.com/〉.
10. Predictive Technology Model, 〈http://www.eas.asu.edu/∼ptm/〉.
11. R. Kumar, V. Kursun, Impact of temperature fluctuations on circuit characteristics in 180 nm and 65 nm CMOS technologies, in: Proceedings of the IEEE International Symposium on Circuits and Systems, May 2006, pp. 410-415.
12. R. Kumar, V. Kursun, A design methodology for temperature variation insensitive low power circuits, in: Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, May 2006, pp. 410-415.
13. Bellaouar A., Fridi A., Elmasry M.J., and Itoh K. Supply voltage scaling for temperature insensitive CMOS circuit operation. IEEE Trans. Circuits Syst. II 45 3 (1998) 415-417
14. M.R. Stan, Optimal voltages and sizing for low power, in: Proceedings of the IEEE International Conference on VLSI Design, January 1999, pp. 428-433.
15. M. Horowitz, T. Indermaur, R. Gonzalez, Low-power digital design, in: Proceedings of the IEEE International Symposium of Low Power Electronics and Design, October 1994, pp. 8-11.
16. Calhoun B.H., Wang A., and Chandrakasan A. Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circuits 40 9 (2005) 1778-1786
17. Gonzalez R., Gordon B., and Horowitz M. Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid-State Circuits 32 8 (1997) 1210-1216
18. V. Kursun, E.G. Friedman, Multi-Voltage CMOS Circuit Design, Wiley, New York, 2006, ISBN #0-470-01023-1.
19. Beadle W.B., et al. Quick Reference Manual for Silicon Integrated Circuit Technology (1985), Wiley, New York
20. Pulfrey D.L., et al. Introduction to Microelectronic Devices (1989), Prentice-Hall, Englewood Cliffs, NJ
21. t technology using dual thickness gate oxide, in: Proceedings of the IEEE VLSI Design and Test Workshop, August 2001, pp. 225-232.
22. Tsividis Y.P. Operation and Modeling of the MOS Transistor (1999), McGraw-Hill, New York