Normal and reverse temperature dependence in variation-tolerant nanoscale systems with high-k dielectrics and metal gates

Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering

Volumn 3 LNICST, Issue , 2009, Pages 14-18

  Wolpert, David ^a   Ampadu, Paul ^a  

^a University of Rochester   (United States)

Author keywords

High k dielectric; Metal gate; Reverse temperature dependence; Variation tolerant

Indexed keywords

ADAPTIVE VOLTAGE SCALING; CRITICAL PATHS; DELAY DEPENDENCE; HIGH-K DIELECTRIC; METAL GATE; NANO-METER REGIMES; NANO-SCALE SYSTEM; NOMINAL VOLTAGE; POLY GATES; REVERSE TEMPERATURE DEPENDENCE; SUPPLY VOLTAGES; TEMPERATURE DEPENDENCE; TEMPERATURE DEPENDENCIES; TEMPERATURE IMPACT; TEMPERATURE INCREASE; TEMPERATURE REGIONS; THERMAL RUNAWAYS; VARIATION-TOLERANT;

DIELECTRIC MATERIALS; TEMPERATURE DISTRIBUTION;

GATE DIELECTRICS;

EID: 77955119433     PISSN: 18678211     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-02427-6_4     Document Type: Conference Paper

References (13)

1. Filanovsky, I.M., Allam, A.: Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications 48, 876-884 (2001) (Pubitemid 32694330)
2. Zhao, W., Cao, Y.: New generation of Predictive Technology Model for sub-45nm early design exploration. IEEE Trans. on Electron Devices 53, 2816-2823 (2006) (Pubitemid 44680679)
3. Zhao, W.: Personal communication (2008)
4. Guillaumot, B., et al.: 75nm damascene metal gate and high-k integration for advanced CMOS devices. In: International Electron Devices Meeting, pp. 355-358 (2002)
5. Cheng, B., et al.: The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's. IEEE Trans. Electron Devices 46, 1537-1544 (1999)
6. Park, C., et al.: Reversal of temperature dependence of integrated circuits operating at very low voltages. In: International Electron Devices Meeting, pp. 71-74 (1995)
7. Bellaouar, A., Fridi, A., Elmasry, M.I., Itoh, K.: Supply voltage scaling for temperature-insensitive CMOS circuit operation. IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing 45, 415-417 (1998) (Pubitemid 128745218)
8. Sato, T., Ichimiya, J., Ono, N., Hachiya, K., Hashimoto, M.: On-chip thermal gradient analysis and temperature attening for SoC design. IEICE Trans. Fundamentals E88-A, 3382-3389 (2005)
9. Martin, S., Flautner, K., Mudge, T., Blaauw, D.: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In: IEEE/ACM Int. Conf. on Computer Aided Design, pp. 721-725 (2002)
10. Tschanz, J., et al.: Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging. In: IEEE Int. Solid-State Circuits Conf., pp. 292-293 (2007)
11. Elgebaly, M., Sachdev, M.: Variation-Aware Adaptive Voltage Scaling System. IEEE Trans. Very Large Scale Integration (VLSI) Systems 15, 560-571 (2007) (Pubitemid 46853323)
12. Lee, C.-C., de Groot, J.: On the thermal stability margins of high-leakage current packaged devices. In: 8th Electronics Packaging Technology Conference, pp. 487-491 (2006)
13. Kim, N.S., et al.: Leakage current: Moore's law meets static power. IEEE Computer 36, 68-75 (2003)