Temperature-insensitive synthesis using multi-Vt libraries

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2008, Pages 5-10

  Calimera, Andrea ^a   Macii, Enrico ^a   Poncino, Massimo ^a   Iris Bahar, R ^b  

^a POLITECNICO DI TORINO   (Italy)

^b Brown University   (United States)

Author keywords

Logic synthesis; Multi threshold voltage; Temperature aware

Indexed keywords

ATMOSPHERIC TEMPERATURE; CLIMATOLOGY; IMAGE SEGMENTATION; LAKES; MOS DEVICES; NETWORKS (CIRCUITS); THRESHOLD VOLTAGE;

BENCHMARK CIRCUITS; CIRCUIT DELAYS; HIGH TEMPERATURES; LEAKAGE POWERS; LOGIC SYNTHESIS; LOW SUPPLY VOLTAGES; MOS CIRCUITS; MULTI-THRESHOLD VOLTAGE; NONMONOTONIC; SIGNIFICANT REDUCTIONS; STATIC POWERS; TEMPERATURE FLUCTUATIONS; TEMPERATURE INCREASES; TEMPERATURE INVERSIONS; WORST CASES;

DELAY CIRCUITS;

EID: 56749083229     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366110.1366116     Document Type: Conference Paper

References (11)

1. A. H. Ajami, K. Banerjee, and M. Pedram. Modeling and analysis of non-uniform substrate temperature effects on global ULSI interconnects. IEEE Trans. on CAD, 24(6):849-861, June 2005.
2. K. Banerjee and A. Mehrotra. Global (interconnect) warming. IEEE Circuits and Devices Magazine, pages 16-32, 2001.
3. L. Benini, E. Macii, M. Poncino, and G. D. Micheli. Telescopic units: A new paradigm for performance optimization of VLSI designs. IEEE Trans. on CAD, 17(3):220-232, Mar. 1998.
4. A. Dasdan and I. Horn. Handling inverted temperature dependence in static timing analysis. ACM Trans. on Design Automation of Electronic Systems, 11(2):306-324, April 2006.
5. S. Ghosh, S. Bhunia, and K. Roy. CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation. IEEE Trans. on CAD, 26(11):1947-1956, Nov. 2007.
6. S. Hassoun and C. Ebeling. Architectural retiming: Pipelining latency-constrained circuits. In ACM/IEEE Design Automation Conf., pages 708-713, June 1996.
7. R. Kumar and V. Kursun. Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits. IEEE Trans. on Circuits and Systems, 53(10):1078-1082, Oct. 2006.
8. S. Nowick. Design of a low-latency asynchronous adder using speculative completion. IEE Proceedings -Computers and Digital Techniques, 143(5):301-307, Sept. 1996.
9. T. Sakurai and A. R. Newton. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal on Solid-State Circuits, 25(2):584-594, Apr. 1990.
10. K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware computer systems: Opportunities and challenges. IEEE Micro, 23(6):52-61, Nov.-Dec. 2003.
11. K. Sundaresan and N. Mahapatra. Accurate energy dissipation and thermal modeling for nanometer-scale buses. In ACM/IEEE Intl. Symp. on High-Performance Computer Architecture, pages 51-60, 2005.