AdNoC: Runtime adaptive network-on-chip architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 2, 2012, Pages 257-269

  Al Faruque, Mohammad Abdullah ^a   Ebi, Thomas ^a   Henkel, Jörg ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

C.1.3.a adaptable architectures; C.1.4.e multicore single chip multiprocessors; C.1.4.g on chip interconnection networks; network on chip (NoC); quality of service (QoS)

Indexed keywords

ADAPTABLE ARCHITECTURE; ADAPTIVE BUFFER; ADAPTIVE SCHEME; ADAPTIVITY; ALLOCATION ALGORITHM; AREA OVERHEAD; DIGITAL-MEDIA APPLICATIONS; GUARANTEED BANDWIDTH; MULTI CORE; NETWORK ON CHIP; NETWORK-ON-CHIP ARCHITECTURES; NOC ARCHITECTURES; NOC DESIGN; ON CHIP INTERCONNECT; ON-CHIP INTERCONNECTION NETWORK; OUTPUT PORTS; RUNTIMES; STATIC NETWORKS; SYSTEM BEHAVIORS; SYSTEM STATE; USER BEHAVIORS; WORST CASE SCENARIO;

ADAPTIVE ALGORITHMS; ARTS COMPUTING; BANDWIDTH; BEHAVIORAL RESEARCH; COMPUTER ARCHITECTURE; DIGITAL STORAGE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; QUALITY OF SERVICE; SERVERS; VLSI CIRCUITS;

NETWORK ARCHITECTURE;

EID: 84856257990     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2094215     Document Type: Article

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