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Volumn 36, Issue 1, 2008, Pages 114-139

QoS-supported on-chip communication for multi-processors

Author keywords

Arbitration; Multi processor; Networks on chips; Quality of services; Service class

Indexed keywords

ARBITRATION; MULTIPROCESSORS; NETWORKS ON CHIPS; SERVICE CLASS;

EID: 38349173862     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-007-0039-0     Document Type: Article
Times cited : (9)

References (23)
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    • Xpipes: A latency insensitive parameterized network-on-chip architecture for multi- processor SoCs
    • M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, and L. Benini, Xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi- Processor SoCs, ICCD, pp. 536-539 (2003).
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    • Dall'Osso, M.1    Biccari, G.2    Giovannini, L.3    Bertozzi, D.4    Benini, L.5
  • 12
    • 27344456043 scopus 로고    scopus 로고
    • Æthereal network on chip: Concepts, architectures, and implementations
    • Sept-Oct
    • Goossens K., Dielissen J., Radulescu A. (Sept-Oct 2005). Æthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design and Test of Computers 22: 414-421
    • (2005) IEEE Design and Test of Computers , vol.22 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 13
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    • QNoC: QoS architecture and design process for network on chip, special issue on networks on chip
    • December
    • E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS Architecture and Design Process for Network on Chip, Special issue on Networks on Chip, The Journal of Systems Architecture, 105-128 (December 2003).
    • (2003) The Journal of Systems Architecture , pp. 105-128
    • Bolotin, E.1    Cidon, I.2    Ginosar, R.3    Kolodny, A.4
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.